qs823.h

u-boot-1.1.6 源码包

 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * TODO flash parameters
 * FLASH organization for Intel Strataflash
 */
#undef  CFG_FLASH_16BIT				/* 32-bit wide flash memory */
#define CFG_MAX_FLASH_BANKS	1		/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	71		/* max number of sectors on one chip */

#define CFG_FLASH_ERASE_TOUT	120000		/* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	500		/* Timeout for Flash Write (in ms) */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16		/* For all MPC8xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4		/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control 11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */

#ifdef CONFIG_WATCHDOG
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWRI | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration 11-6
 *-----------------------------------------------------------------------
 */
#define CFG_SIUMCR	(SIUMCR_DLK | SIUMCR_DPC | SIUMCR_MPRE | SIUMCR_MLRC01 | SIUMCR_GB5E)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control 11-26
 *-----------------------------------------------------------------------
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register 11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control 11-31
 *-----------------------------------------------------------------------
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
 *-----------------------------------------------------------------------
 */

/* MF (Multiplication Factor of SPLL) */
/* Sets the QS823 to specified clock from 32KHz clock at EXTAL. */
#define vPLPRCR_MF	((CONFIG_CLOCK_MULT+1) << 20)
#define CFG_PLPRCR	(vPLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | PLPRCR_LOLRE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 */
#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG00)
#define CFG_BRGCLK_PRESCALE	1
#endif

#if defined(CONFIG_CLOCK_66MHZ)
#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF00 | SCCR_DFBRG01)
#define CFG_BRGCLK_PRESCALE	4
#endif

#if defined(CONFIG_CLOCK_80MHZ)
#define CFG_SCCR		(SCCR_TBS | SCCR_EBDF01 | SCCR_DFBRG01)
#define CFG_BRGCLK_PRESCALE	4
#endif

#define SCCR_MASK		CFG_SCCR

/*-----------------------------------------------------------------------
 * Debug Enable Register
 * 0x73E67C0F - All interrupts handled by BDM
 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
 *-----------------------------------------------------------------------
#define CFG_DER			0x73E67C0F
#define CFG_DER			0x0082400F

 #-------------------------------------------------------------------------
 # Program the Debug Enable Register (DER). This register provides the user
 # with the reason for entering into the debug mode. We want all conditions
 # to end up as an exception. We don't want to enter into debug mode for
 # any condition. See the back of of the Development Support section of the
 # MPC860 User Manual for a description of this register.
 #-------------------------------------------------------------------------
*/
#define CFG_DER			0

/*-----------------------------------------------------------------------
 * Memory Controller Initialization Constants
 *-----------------------------------------------------------------------
 */

/*
 * BR0 and OR0 (AMD dual FLASH devices)
 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
 */
#define CFG_PRELIM_OR_AM
#define CFG_OR_TIMING_FLASH

/*
 *-----------------------------------------------------------------------
 * Base Register 0 (BR0): Bank 0 is assigned to the 8Mbyte (2M X 32)
 *                        flash that resides on the QS823.
 *-----------------------------------------------------------------------
 */

/* BA (Base Address) = 0xFF80+0b for a total of 17 bits. 17 bit base addr */
/*                     represents a minumum 32K block size. */
#define vBR0_BA			((0xFF80 << 16) + (0 << 15))
#define CFG_BR0_PRELIM		(vBR0_BA | BR_V)

/* AM (Address Mask) = 0xFF80+0b = We've masked the upper 9 bits        */
/*                                 which defines a 8 Mbyte memory block. */
#define vOR0_AM			((0xFF80 << 16) + (0 << 15))

#if defined(CONFIG_CLOCK_50MHZ) || defined(CONFIG_CLOCK_80MHZ)
/*  0101 = Add a 5 clock cycle wait state */
#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | 0R_ACS_DIV4 | OR_BI | OR_SCY_5_CLK)
#endif

#if defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_66MHZ)
/*  0011 = Add a 3 clock cycle wait state */
/*  29.8ns clock * (3 + 2) = 149ns cycle time */
#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK)
#endif

#if defined(CONFIG_CLOCK_16MHZ)
/*  0010 = Add a 2 clock cycle wait state */
#define CFG_OR0_PRELIM		(vOR0_AM | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_2_CLK)
#endif

/*
 * BR1 and OR1 (SDRAM)
 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
 * Base Address = 0x00000000 - 0x01FF_FFFF (32M After relocation)
 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
 */

#define SDRAM_BASE		0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */

/* AM (Address Mask) = 0xF800+0b = We've masked the upper 5 bits which
 *                                 represents a 128 Mbyte block the DRAM in
 *                                 this address base.
 */
#define vOR1_AM			((0xF800 << 16) + (0 << 15))
#define vBR1_BA			((0x0000 << 16) + (0 << 15))
#define CFG_OR1			(vOR1_AM | OR_CSNT_SAM | OR_BI)
#define CFG_BR1			(vBR1_BA | BR_MS_UPMA | BR_V)

/* Machine A Mode Register */

/* PTA Periodic Timer A */

#if defined(CONFIG_CLOCK_80MHZ)
#define vMAMR_PTA		(19 << 24)
#endif

#if defined(CONFIG_CLOCK_66MHZ)
#define vMAMR_PTA		(16 << 24)
#endif

#if defined(CONFIG_CLOCK_50MHZ)
#define vMAMR_PTA		(195 << 24)
#endif

#if defined(CONFIG_CLOCK_33MHZ)
#define vMAMR_PTA		(131 << 24)
#endif

#if defined(CONFIG_CLOCK_16MHZ)
#define vMAMR_PTA		(65 << 24)
#endif

/* For boards with 16M of SDRAM */
#define SDRAM_16M_MAX_SIZE	0x01000000	/* max 16MB SDRAM */
#define CFG_16M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_0 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A11 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)

/* For boards with 32M of SDRAM */
#define SDRAM_32M_MAX_SIZE	0x02000000	/* max 32MB SDRAM */
#define CFG_32M_MAMR 		(vMAMR_PTA | MAMR_AMA_TYPE_1 | MAMR_DSA_2_CYCL | MAMR_G0CLA_A10 |\
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)


/* Memory Periodic Timer Prescaler Register */

#if defined(CONFIG_CLOCK_66MHZ) || defined(CONFIG_CLOCK_80MHZ)
/* Divide by 32 */
#define CFG_MPTPR		0x02
#endif

#if defined(CONFIG_CLOCK_16MHZ) || defined(CONFIG_CLOCK_33MHZ) || defined(CONFIG_CLOCK_50MHZ)
/* Divide by 16 */
#define CFG_MPTPR		0x04
#endif

/*
 * BR2 and OR2 (Unused)
 * Base address = 0xF020_0000 - 0xF020_0FFF
 *
 */
#define CFG_OR2_PRELIM		0xFFF00000
#define CFG_BR2_PRELIM		0xF0200000

/*
 * BR3 and OR3 (External Bus CS3)
 * Base address = 0xF030_0000 - 0xF030_0FFF
 *
 */
#define CFG_OR3_PRELIM		0xFFF00000
#define CFG_BR3_PRELIM		0xF0300000

/*
 * BR4 and OR4 (External Bus CS3)
 * Base address = 0xF040_0000 - 0xF040_0FFF
 *
 */
#define CFG_OR4_PRELIM		0xFFF00000
#define CFG_BR4_PRELIM		0xF0400000


/*
 * BR4 and OR4 (External Bus CS3)
 * Base address = 0xF050_0000 - 0xF050_0FFF
 *
 */
#define CFG_OR5_PRELIM		0xFFF00000
#define CFG_BR5_PRELIM		0xF0500000

/*
 * BR6 and OR6 (Unused)
 * Base address = 0xF060_0000 - 0xF060_0FFF
 *
 */
#define CFG_OR6_PRELIM		0xFFF00000
#define CFG_BR6_PRELIM		0xF0600000

/*
 * BR7 and OR7 (Unused)
 * Base address = 0xF070_0000 - 0xF070_0FFF
 *
 */
#define CFG_OR7_PRELIM		0xFFF00000
#define CFG_BR7_PRELIM		0xF0700000

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM		0x02	/* Software reboot */

/*
 * Sanity checks
 */
#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
#endif

#endif /* __CONFIG_H */