📄 ids8247.h
字号:
{ \ *(((volatile __u8 *)nandptr) + 0x8) = 0; \} while(0)#define NAND_CTL_SETALE(nandptr) do \{ \ *(((volatile __u8 *)nandptr) + 0x9) = 0; \} while(0)#define NAND_CTL_CLRCLE(nandptr) do \{ \ *(((volatile __u8 *)nandptr) + 0x8) = 0; \} while(0)#define NAND_CTL_SETCLE(nandptr) do \{ \ *(((volatile __u8 *)nandptr) + 0xa) = 0; \} while(0)#ifdef NAND_NO_RB/* constant delay (see also tR in the datasheet) */#define NAND_WAIT_READY(nand) do { \ udelay(12); \} while (0)#else/* use the R/B pin */#endif#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))#endif /* CFG_CMD_NAND *//*----------------------------------------------------------------------- * Hard Reset Configuration Words * * if you change bits in the HRCW, you must also change the CFG_* * defines for the various registers affected by the HRCW e.g. changing * HRCW_DPPCxx requires you to also change CFG_SIUMCR. */#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)/* no slaves so just fill with zeros */#define CFG_HRCW_SLAVE1 0#define CFG_HRCW_SLAVE2 0#define CFG_HRCW_SLAVE3 0#define CFG_HRCW_SLAVE4 0#define CFG_HRCW_SLAVE5 0#define CFG_HRCW_SLAVE6 0#define CFG_HRCW_SLAVE7 0/*----------------------------------------------------------------------- * Internal Memory Mapped Register */#define CFG_IMMR 0xF0000000/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */#define CFG_INIT_RAM_ADDR CFG_IMMR#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET/*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 * * 60x SDRAM is mapped at CFG_SDRAM_BASE */#define CFG_SDRAM_BASE 0x00000000#define CFG_FLASH_BASE CFG_FLASH0_BASE#define CFG_MONITOR_BASE TEXT_BASE#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*//* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/#define BOOTFLAG_WARM 0x02 /* Software reboot *//*----------------------------------------------------------------------- * Cache Configuration */#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */#if (CONFIG_COMMANDS & CFG_CMD_KGDB)# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */#endif/*----------------------------------------------------------------------- * HIDx - Hardware Implementation-dependent Registers 2-11 *----------------------------------------------------------------------- * HID0 also contains cache control - initially enable both caches and * invalidate contents, then the final state leaves only the instruction * cache enabled. Note that Power-On and Hard reset invalidate the caches, * but Soft reset does not. * * HID1 has only read-only information - nothing to set. */#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)#define CFG_HID0_FINAL 0#define CFG_HID2 0/*----------------------------------------------------------------------- * RMR - Reset Mode Register 5-5 *----------------------------------------------------------------------- * turn on Checkstop Reset Enable */#define CFG_RMR 0/*----------------------------------------------------------------------- * BCR - Bus Configuration 4-25 *----------------------------------------------------------------------- */#define CFG_BCR 0/*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 4-31 *----------------------------------------------------------------------- */#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)/*----------------------------------------------------------------------- * SYPCR - System Protection Control 4-35 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable */#if defined(CONFIG_WATCHDOG)#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)#else#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ SYPCR_SWRI|SYPCR_SWP)#endif /* CONFIG_WATCHDOG *//*----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control 4-40 *----------------------------------------------------------------------- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, * and enable Time Counter */#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control 4-42 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable * Periodic timer */#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)/*----------------------------------------------------------------------- * SCCR - System Clock Control 9-8 *----------------------------------------------------------------------- * Ensure DFBRG is Divide by 16 */#define CFG_SCCR (0x00000028 | SCCR_DFBRG01)/*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration 13-7 *----------------------------------------------------------------------- */#define CFG_RCCR 0/* * Init Memory Controller: * * Bank Bus Machine PortSz Device * ---- --- ------- ------ ------ * 0 60x GPCM 16 bit FLASH * 1 60x GPCM 8 bit NAND * 2 60x SDRAM 32 bit SDRAM * 3 60x GPCM 8 bit UART * */#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB *//* Minimum mask to separate preliminary * address ranges for CS[0:2] */#define CFG_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */#define CFG_MPTPR 0x6600/*----------------------------------------------------------------------------- * Address for Mode Register Set (MRS) command *----------------------------------------------------------------------------- */#define CFG_MRS_OFFS 0x00000110/* Bank 0 - FLASH */#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ BRx_PS_8 |\ BRx_MS_GPCM_P |\ BRx_V)#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ ORxG_SCY_6_CLK )#if (CONFIG_COMMANDS & CFG_CMD_NAND)/* Bank 1 - NAND Flash*/#define CFG_NAND_BASE CFG_NAND0_BASE#define CFG_NAND_SIZE 0x8000#define CFG_OR_TIMING_NAND 0x000036#define CFG_BR1_PRELIM ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )#endif/* Bank 2 - 60x bus SDRAM */#define CFG_PSRT 0x20#define CFG_LSRT 0x20#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ BRx_PS_32 |\ BRx_MS_SDRAM_P |\ BRx_V)#define CFG_OR2_PRELIM CFG_OR2/* SDRAM initialization values*/#define CFG_OR2 ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ ORxS_BPD_4 |\ ORxS_ROWST_PBI0_A10 |\ ORxS_NUMR_12)#define CFG_PSDMR (PSDMR_SDAM_A13_IS_A5 |\ PSDMR_BSMA_A15_A17 |\ PSDMR_SDA10_PBI0_A11 |\ PSDMR_RFRC_5_CLK |\ PSDMR_PRETOACT_2W |\ PSDMR_ACTTORW_2W |\ PSDMR_BL |\ PSDMR_LDOTOPRE_2C |\ PSDMR_WRC_3C |\ PSDMR_CL_3)/* Bank 3 - UART*/#define CFG_BR3_PRELIM ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V )#define CFG_OR3_PRELIM (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )#endif /* __CONFIG_H */⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -