lan91c96.h

u-boot-1.1.6 源码包

 *	Bank 1 Register Map in I/O Space
 ****************************************************************************
 */
#define LAN91C96_CONFIG       0        /* Configuration Register */
#define LAN91C96_BASE         2        /* Base Address Register */
#define LAN91C96_IA0          4        /* Individual Address Register - 0 */
#define LAN91C96_IA1          5        /* Individual Address Register - 1 */
#define LAN91C96_IA2          6        /* Individual Address Register - 2 */
#define LAN91C96_IA3          7        /* Individual Address Register - 3 */
#define LAN91C96_IA4          8        /* Individual Address Register - 4 */
#define LAN91C96_IA5          9        /* Individual Address Register - 5 */
#define LAN91C96_GEN_PURPOSE  10       /* General Address Registers */
#define LAN91C96_CONTROL      12       /* Control Register */

/*
 ****************************************************************************
 *	Configuration Register - Bank 1 - Offset 0
 ****************************************************************************
 */
#define LAN91C96_CR_INT_SEL0      (0x1U << 1)
#define LAN91C96_CR_INT_SEL1      (0x1U << 2)
#define LAN91C96_CR_RES           (0x3U << 3)
#define LAN91C96_CR_DIS_LINK      (0x1U << 6)
#define LAN91C96_CR_16BIT         (0x1U << 7)
#define LAN91C96_CR_AUI_SELECT    (0x1U << 8)
#define LAN91C96_CR_SET_SQLCH     (0x1U << 9)
#define LAN91C96_CR_FULL_STEP     (0x1U << 10)
#define LAN91C96_CR_NO_WAIT       (0x1U << 12)

/*
 ****************************************************************************
 *	Base Address Register - Bank 1 - Offset 2
 ****************************************************************************
 */
#define LAN91C96_BAR_RA_BITS      (0x27U << 0)
#define LAN91C96_BAR_ROM_SIZE     (0x1U << 6)
#define LAN91C96_BAR_A_BITS       (0xFFU << 8)

/*
 ****************************************************************************
 *	Control Register - Bank 1 - Offset 12
 ****************************************************************************
 */
#define LAN91C96_CTR_STORE        (0x1U << 0)
#define LAN91C96_CTR_RELOAD       (0x1U << 1)
#define LAN91C96_CTR_EEPROM       (0x1U << 2)
#define LAN91C96_CTR_TE_ENABLE    (0x1U << 5)
#define LAN91C96_CTR_CR_ENABLE    (0x1U << 6)
#define LAN91C96_CTR_LE_ENABLE    (0x1U << 7)
#define LAN91C96_CTR_BIT_8        (0x1U << 8)
#define LAN91C96_CTR_AUTO_RELEASE (0x1U << 11)
#define LAN91C96_CTR_WAKEUP_EN    (0x1U << 12)
#define LAN91C96_CTR_PWRDN        (0x1U << 13)
#define LAN91C96_CTR_RCV_BAD      (0x1U << 14)

/*
 ****************************************************************************
 *	Bank 2 Register Map in I/O Space
 ****************************************************************************
 */
#define LAN91C96_MMU            0      /* MMU Command Register */
#define LAN91C96_AUTO_TX_START  1      /* Auto Tx Start Register */
#define LAN91C96_PNR            2      /* Packet Number Register */
#define LAN91C96_ARR            3      /* Allocation Result Register */
#define LAN91C96_FIFO           4      /* FIFO Ports Register */
#define LAN91C96_POINTER        6      /* Pointer Register */
#define LAN91C96_DATA_HIGH      8      /* Data High Register */
#define LAN91C96_DATA_LOW       10     /* Data Low Register */
#define LAN91C96_INT_STATS      12     /* Interrupt Status Register - RO */
#define LAN91C96_INT_ACK        12     /* Interrupt Acknowledge Register -WO */
#define LAN91C96_INT_MASK       13     /* Interrupt Mask Register */

/*
 ****************************************************************************
 *	MMU Command Register - Bank 2 - Offset 0
 ****************************************************************************
 */
#define LAN91C96_MMUCR_NO_BUSY    (0x1U << 0)
#define LAN91C96_MMUCR_N1         (0x1U << 1)
#define LAN91C96_MMUCR_N2         (0x1U << 2)
#define LAN91C96_MMUCR_COMMAND    (0xFU << 4)
#define LAN91C96_MMUCR_ALLOC_TX   (0x2U << 4)    /* WXYZ = 0010 */
#define LAN91C96_MMUCR_RESET_MMU  (0x4U << 4)    /* WXYZ = 0100 */
#define LAN91C96_MMUCR_REMOVE_RX  (0x6U << 4)    /* WXYZ = 0110 */
#define LAN91C96_MMUCR_REMOVE_TX  (0x7U << 4)    /* WXYZ = 0111 */
#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4)    /* WXYZ = 1000 */
#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4)    /* WXYZ = 1010 */
#define LAN91C96_MMUCR_ENQUEUE    (0xCU << 4)    /* WXYZ = 1100 */
#define LAN91C96_MMUCR_RESET_TX   (0xEU << 4)    /* WXYZ = 1110 */

/*
 ****************************************************************************
 *	Auto Tx Start Register - Bank 2 - Offset 1
 ****************************************************************************
 */
#define LAN91C96_AUTOTX           (0xFFU << 0)

/*
 ****************************************************************************
 *	Packet Number Register - Bank 2 - Offset 2
 ****************************************************************************
 */
#define LAN91C96_PNR_TX           (0x1FU << 0)

/*
 ****************************************************************************
 *	Allocation Result Register - Bank 2 - Offset 3
 ****************************************************************************
 */
#define LAN91C96_ARR_ALLOC_PN     (0x7FU << 0)
#define LAN91C96_ARR_FAILED       (0x1U << 7)

/*
 ****************************************************************************
 *	FIFO Ports Register - Bank 2 - Offset 4
 ****************************************************************************
 */
#define LAN91C96_FIFO_TX_DONE_PN  (0x1FU << 0)
#define LAN91C96_FIFO_TEMPTY      (0x1U << 7)
#define LAN91C96_FIFO_RX_DONE_PN  (0x1FU << 8)
#define LAN91C96_FIFO_RXEMPTY     (0x1U << 15)

/*
 ****************************************************************************
 *	Pointer Register - Bank 2 - Offset 6
 ****************************************************************************
 */
#define LAN91C96_PTR_LOW          (0xFFU << 0)
#define LAN91C96_PTR_HIGH         (0x7U << 8)
#define LAN91C96_PTR_AUTO_TX      (0x1U << 11)
#define LAN91C96_PTR_ETEN         (0x1U << 12)
#define LAN91C96_PTR_READ         (0x1U << 13)
#define LAN91C96_PTR_AUTO_INCR    (0x1U << 14)
#define LAN91C96_PTR_RCV          (0x1U << 15)

#define LAN91C96_PTR_RX_FRAME     (LAN91C96_PTR_RCV       |    \
				   LAN91C96_PTR_AUTO_INCR |    \
				   LAN91C96_PTR_READ)

/*
 ****************************************************************************
 *	Data Register - Bank 2 - Offset 8
 ****************************************************************************
 */
#define LAN91C96_CONTROL_CRC      (0x1U << 4)    /* CRC bit */
#define LAN91C96_CONTROL_ODD      (0x1U << 5)    /* ODD bit */

/*
 ****************************************************************************
 *	Interrupt Status Register - Bank 2 - Offset 12
 ****************************************************************************
 */
#define LAN91C96_IST_RCV_INT      (0x1U << 0)
#define LAN91C96_IST_TX_INT       (0x1U << 1)
#define LAN91C96_IST_TX_EMPTY_INT (0x1U << 2)
#define LAN91C96_IST_ALLOC_INT    (0x1U << 3)
#define LAN91C96_IST_RX_OVRN_INT  (0x1U << 4)
#define LAN91C96_IST_EPH_INT      (0x1U << 5)
#define LAN91C96_IST_ERCV_INT     (0x1U << 6)
#define LAN91C96_IST_RX_IDLE_INT  (0x1U << 7)

/*
 ****************************************************************************
 *	Interrupt Acknowledge Register - Bank 2 - Offset 12
 ****************************************************************************
 */
#define LAN91C96_ACK_TX_INT       (0x1U << 1)
#define LAN91C96_ACK_TX_EMPTY_INT (0x1U << 2)
#define LAN91C96_ACK_RX_OVRN_INT  (0x1U << 4)
#define LAN91C96_ACK_ERCV_INT     (0x1U << 6)

/*
 ****************************************************************************
 *	Interrupt Mask Register - Bank 2 - Offset 13
 ****************************************************************************
 */
#define LAN91C96_MSK_RCV_INT      (0x1U << 0)
#define LAN91C96_MSK_TX_INT       (0x1U << 1)
#define LAN91C96_MSK_TX_EMPTY_INT (0x1U << 2)
#define LAN91C96_MSK_ALLOC_INT    (0x1U << 3)
#define LAN91C96_MSK_RX_OVRN_INT  (0x1U << 4)
#define LAN91C96_MSK_EPH_INT      (0x1U << 5)
#define LAN91C96_MSK_ERCV_INT     (0x1U << 6)
#define LAN91C96_MSK_TX_IDLE_INT  (0x1U << 7)

/*
 ****************************************************************************
 *	Bank 3 Register Map in I/O Space
 **************************************************************************
 */
#define LAN91C96_MGMT_MDO         (0x1U << 0)
#define LAN91C96_MGMT_MDI         (0x1U << 1)
#define LAN91C96_MGMT_MCLK        (0x1U << 2)
#define LAN91C96_MGMT_MDOE        (0x1U << 3)
#define LAN91C96_MGMT_LOW_ID      (0x3U << 4)
#define LAN91C96_MGMT_IOS0        (0x1U << 8)
#define LAN91C96_MGMT_IOS1        (0x1U << 9)
#define LAN91C96_MGMT_IOS2        (0x1U << 10)
#define LAN91C96_MGMT_nXNDEC      (0x1U << 11)
#define LAN91C96_MGMT_HIGH_ID     (0x3U << 12)

/*
 ****************************************************************************
 *	Revision Register - Bank 3 - Offset 10
 ****************************************************************************
 */
#define LAN91C96_REV_REVID        (0xFU << 0)
#define LAN91C96_REV_CHIPID       (0xFU << 4)

/*
 ****************************************************************************
 *	Early RCV Register - Bank 3 - Offset 12
 ****************************************************************************
 */
#define LAN91C96_ERCV_THRESHOLD   (0x1FU << 0)
#define LAN91C96_ERCV_RCV_DISCRD  (0x1U << 7)

/*
 ****************************************************************************
 *	PCMCIA Configuration Registers
 ****************************************************************************
 */
#define LAN91C96_ECOR    0x8000        /* Ethernet Configuration Register */
#define LAN91C96_ECSR    0x8002        /* Ethernet Configuration and Status */

/*
 ****************************************************************************
 *	PCMCIA Ethernet Configuration Option Register (ECOR)
 ****************************************************************************
 */
#define LAN91C96_ECOR_ENABLE       (0x1U << 0)
#define LAN91C96_ECOR_WR_ATTRIB    (0x1U << 2)
#define LAN91C96_ECOR_LEVEL_REQ    (0x1U << 6)
#define LAN91C96_ECOR_SRESET       (0x1U << 7)

/*
 ****************************************************************************
 *	PCMCIA Ethernet Configuration and Status Register (ECSR)
 ****************************************************************************
 */
#define LAN91C96_ECSR_INTR        (0x1U << 1)
#define LAN91C96_ECSR_PWRDWN      (0x1U << 2)
#define LAN91C96_ECSR_IOIS8       (0x1U << 5)

/*
 ****************************************************************************
 *	Receive Frame Status Word - See page 38 of the LAN91C96 specification.
 ****************************************************************************
 */
#define LAN91C96_TOO_SHORT        (0x1U << 10)
#define LAN91C96_TOO_LONG         (0x1U << 11)
#define LAN91C96_ODD_FRM          (0x1U << 12)
#define LAN91C96_BAD_CRC          (0x1U << 13)
#define LAN91C96_BROD_CAST        (0x1U << 14)
#define LAN91C96_ALGN_ERR         (0x1U << 15)

#define FRAME_FILTER              (LAN91C96_TOO_SHORT | LAN91C96_TOO_LONG  | LAN91C96_BAD_CRC   | LAN91C96_ALGN_ERR)

/*
 ****************************************************************************
 *	Default MAC Address
 ****************************************************************************
 */
#define MAC_DEF_HI  0x0800
#define MAC_DEF_MED 0x3333
#define MAC_DEF_LO  0x0100

/*
 ****************************************************************************
 *	Default I/O Signature - 0x33
 ****************************************************************************
 */
#define LAN91C96_LOW_SIGNATURE        (0x33U << 0)
#define LAN91C96_HIGH_SIGNATURE       (0x33U << 8)
#define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE)

#define LAN91C96_MAX_PAGES     6        /* Maximum number of 256 pages. */
#define ETHERNET_MAX_LENGTH 1514


/*-------------------------------------------------------------------------
 *  I define some macros to make it easier to do somewhat common
 * or slightly complicated, repeated tasks.
 *-------------------------------------------------------------------------
 */

/* select a register bank, 0 to 3  */

#define SMC_SELECT_BANK(x)  { SMC_outw( x, LAN91C96_BANK_SELECT ); }

/* this enables an interrupt in the interrupt mask register */
#define SMC_ENABLE_INT(x) {\
		unsigned char mask;\
		SMC_SELECT_BANK(2);\
		mask = SMC_inb( LAN91C96_INT_MASK );\
		mask |= (x);\
		SMC_outb( mask, LAN91C96_INT_MASK ); \
}

/* this disables an interrupt from the interrupt mask register */

#define SMC_DISABLE_INT(x) {\
		unsigned char mask;\
		SMC_SELECT_BANK(2);\
		mask = SMC_inb( LAN91C96_INT_MASK );\
		mask &= ~(x);\
		SMC_outb( mask, LAN91C96_INT_MASK ); \
}

/*----------------------------------------------------------------------
 * Define the interrupts that I want to receive from the card
 *
 * I want:
 *  LAN91C96_IST_EPH_INT, for nasty errors
 *  LAN91C96_IST_RCV_INT, for happy received packets
 *  LAN91C96_IST_RX_OVRN_INT, because I have to kick the receiver
 *-------------------------------------------------------------------------
 */
#define SMC_INTERRUPT_MASK   (LAN91C96_IST_EPH_INT | LAN91C96_IST_RX_OVRN_INT | LAN91C96_IST_RCV_INT)

#endif  /* _LAN91C96_H_ */