lan91c96.h

u-boot-1.1.6 源码包

/*------------------------------------------------------------------------
 * lan91c96.h
 *
 * (C) Copyright 2002
 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
 * Rolf Offermanns <[e-mail]>
 * Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
 *       Developed by Simple Network Magic Corporation (SNMC)
 * Copyright (C) 1996 by Erik Stahlman (ES)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 * This file contains register information and access macros for
 * the LAN91C96 single chip ethernet controller.  It is a modified
 * version of the smc9111.h file.
 *
 * Information contained in this file was obtained from the LAN91C96
 * manual from SMC. To get a copy, if you really want one, you can find
 * information under www.smsc.com.
 *
 * Authors
 * 	Erik Stahlman				( [e-mail] )
 *	Daris A Nevil				( [e-mail] )
 *
 * History
 * 04/30/03	Mathijs Haarman		Modified smc91111.h (u-boot version)
 *		                        for lan91c96
 *-------------------------------------------------------------------------
 */
#ifndef _LAN91C96_H_
#define _LAN91C96_H_

#include <asm/types.h>
#include <asm/io.h>
#include <config.h>

/*
 * This function may be called by the board specific initialisation code
 * in order to override the default mac address.
 */

void smc_set_mac_addr(const unsigned char *addr);


/* I want some simple types */

typedef unsigned char			byte;
typedef unsigned short			word;
typedef unsigned long int 		dword;

/*
 * DEBUGGING LEVELS
 *
 * 0 for normal operation
 * 1 for slightly more details
 * >2 for various levels of increasingly useless information
 *    2 for interrupt tracking, status flags
 *    3 for packet info
 *    4 for complete packet dumps
 */
/*#define SMC_DEBUG 0 */

/* Because of bank switching, the LAN91xxx uses only 16 I/O ports */

#define	SMC_IO_EXTENT	16

#ifdef CONFIG_PXA250

#ifdef	CONFIG_LUBBOCK
#define	SMC_IO_SHIFT	2
#undef	USE_32_BIT

#else
#define	SMC_IO_SHIFT	0
#endif

#define	SMCREG(r)	(SMC_BASE_ADDRESS+((r)<<SMC_IO_SHIFT))

#define	SMC_inl(r) 	(*((volatile dword *)SMCREG(r)))
#define	SMC_inw(r) 	(*((volatile word *)SMCREG(r)))
#define SMC_inb(p) ({ \
	unsigned int __p = p; \
	unsigned int __v = SMC_inw(__p & ~1); \
	if (__p & 1) __v >>= 8; \
	else __v &= 0xff; \
	__v; })

#define	SMC_outl(d,r)	(*((volatile dword *)SMCREG(r)) = d)
#define	SMC_outw(d,r)	(*((volatile word *)SMCREG(r)) = d)
#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
				word __w = SMC_inw((r)&~1);  \
				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
				__w |= ((r)&1) ? __d<<8 : __d;  \
				SMC_outw(__w,(r)&~1);  \
			})

#define SMC_outsl(r,b,l)	({	int __i; \
					dword *__b2; \
					__b2 = (dword *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outl( *(__b2 + __i), r ); \
					} \
				})

#define SMC_outsw(r,b,l)	({	int __i; \
					word *__b2; \
					__b2 = (word *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outw( *(__b2 + __i), r ); \
					} \
				})

#define SMC_insl(r,b,l) 	({	int __i ;  \
					dword *__b2;  \
					__b2 = (dword *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inl(r);  \
					  SMC_inl(0);  \
					};  \
				})

#define SMC_insw(r,b,l) 	({	int __i ;  \
					word *__b2;  \
					__b2 = (word *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inw(r);  \
					  SMC_inw(0);  \
					};  \
				})

#define SMC_insb(r,b,l) 	({	int __i ;  \
					byte *__b2;  \
					__b2 = (byte *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inb(r);  \
					  SMC_inb(0);  \
					};  \
				})

#else /* if not CONFIG_PXA250 */

/*
 * We have only 16 Bit PCMCIA access on Socket 0
 */

#define	SMC_inw(r) 	(*((volatile word *)(SMC_BASE_ADDRESS+(r))))
#define  SMC_inb(r)	(((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF)

#define	SMC_outw(d,r)	(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d)
#define	SMC_outb(d,r)	({	word __d = (byte)(d);  \
				word __w = SMC_inw((r)&~1);  \
				__w &= ((r)&1) ? 0x00FF : 0xFF00;  \
				__w |= ((r)&1) ? __d<<8 : __d;  \
				SMC_outw(__w,(r)&~1);  \
			})
#if 0
#define	SMC_outsw(r,b,l)	outsw(SMC_BASE_ADDRESS+(r), (b), (l))
#else
#define SMC_outsw(r,b,l)	({	int __i; \
					word *__b2; \
					__b2 = (word *) b; \
					for (__i = 0; __i < l; __i++) { \
					    SMC_outw( *(__b2 + __i), r); \
					} \
				})
#endif

#if 0
#define	SMC_insw(r,b,l) 	insw(SMC_BASE_ADDRESS+(r), (b), (l))
#else
#define SMC_insw(r,b,l) 	({	int __i ;  \
					word *__b2;  \
					__b2 = (word *) b;  \
					for (__i = 0; __i < l; __i++) {  \
					  *(__b2 + __i) = SMC_inw(r);  \
					  SMC_inw(0);  \
					};  \
				})
#endif

#endif

/*
 ****************************************************************************
 *	Bank Select Field
 ****************************************************************************
 */
#define LAN91C96_BANK_SELECT  14       /* Bank Select Register */
#define LAN91C96_BANKSELECT (0x3UC << 0)
#define BANK0               0x00
#define BANK1               0x01
#define BANK2               0x02
#define BANK3               0x03
#define BANK4               0x04

/*
 ****************************************************************************
 *	EEPROM Addresses.
 ****************************************************************************
 */
#define EEPROM_MAC_OFFSET_1    0x6020
#define EEPROM_MAC_OFFSET_2    0x6021
#define EEPROM_MAC_OFFSET_3    0x6022

/*
 ****************************************************************************
 *	Bank 0 Register Map in I/O Space
 ****************************************************************************
 */
#define LAN91C96_TCR          0        /* Transmit Control Register */
#define LAN91C96_EPH_STATUS   2        /* EPH Status Register */
#define LAN91C96_RCR          4        /* Receive Control Register */
#define LAN91C96_COUNTER      6        /* Counter Register */
#define LAN91C96_MIR          8        /* Memory Information Register */
#define LAN91C96_MCR          10       /* Memory Configuration Register */

/*
 ****************************************************************************
 *	Transmit Control Register - Bank 0 - Offset 0
 ****************************************************************************
 */
#define LAN91C96_TCR_TXENA        (0x1U << 0)
#define LAN91C96_TCR_LOOP         (0x1U << 1)
#define LAN91C96_TCR_FORCOL       (0x1U << 2)
#define LAN91C96_TCR_TXP_EN       (0x1U << 3)
#define LAN91C96_TCR_PAD_EN       (0x1U << 7)
#define LAN91C96_TCR_NOCRC        (0x1U << 8)
#define LAN91C96_TCR_MON_CSN      (0x1U << 10)
#define LAN91C96_TCR_FDUPLX       (0x1U << 11)
#define LAN91C96_TCR_STP_SQET     (0x1U << 12)
#define LAN91C96_TCR_EPH_LOOP     (0x1U << 13)
#define LAN91C96_TCR_ETEN_TYPE    (0x1U << 14)
#define LAN91C96_TCR_FDSE         (0x1U << 15)

/*
 ****************************************************************************
 *	EPH Status Register - Bank 0 - Offset 2
 ****************************************************************************
 */
#define LAN91C96_EPHSR_TX_SUC     (0x1U << 0)
#define LAN91C96_EPHSR_SNGL_COL   (0x1U << 1)
#define LAN91C96_EPHSR_MUL_COL    (0x1U << 2)
#define LAN91C96_EPHSR_LTX_MULT   (0x1U << 3)
#define LAN91C96_EPHSR_16COL      (0x1U << 4)
#define LAN91C96_EPHSR_SQET       (0x1U << 5)
#define LAN91C96_EPHSR_LTX_BRD    (0x1U << 6)
#define LAN91C96_EPHSR_TX_DEFR    (0x1U << 7)
#define LAN91C96_EPHSR_WAKEUP     (0x1U << 8)
#define LAN91C96_EPHSR_LATCOL     (0x1U << 9)
#define LAN91C96_EPHSR_LOST_CARR  (0x1U << 10)
#define LAN91C96_EPHSR_EXC_DEF    (0x1U << 11)
#define LAN91C96_EPHSR_CTR_ROL    (0x1U << 12)

#define LAN91C96_EPHSR_LINK_OK    (0x1U << 14)
#define LAN91C96_EPHSR_TX_UNRN    (0x1U << 15)

#define LAN91C96_EPHSR_ERRORS     (LAN91C96_EPHSR_SNGL_COL  |    \
				   LAN91C96_EPHSR_MUL_COL   |    \
				   LAN91C96_EPHSR_16COL     |    \
				   LAN91C96_EPHSR_SQET      |    \
				   LAN91C96_EPHSR_TX_DEFR   |    \
				   LAN91C96_EPHSR_LATCOL    |    \
				   LAN91C96_EPHSR_LOST_CARR |    \
				   LAN91C96_EPHSR_EXC_DEF   |    \
				   LAN91C96_EPHSR_LINK_OK   |    \
				   LAN91C96_EPHSR_TX_UNRN)

/*
 ****************************************************************************
 *	Receive Control Register - Bank 0 - Offset 4
 ****************************************************************************
 */
#define LAN91C96_RCR_RX_ABORT     (0x1U << 0)
#define LAN91C96_RCR_PRMS         (0x1U << 1)
#define LAN91C96_RCR_ALMUL        (0x1U << 2)
#define LAN91C96_RCR_RXEN         (0x1U << 8)
#define LAN91C96_RCR_STRIP_CRC    (0x1U << 9)
#define LAN91C96_RCR_FILT_CAR     (0x1U << 14)
#define LAN91C96_RCR_SOFT_RST     (0x1U << 15)

/*
 ****************************************************************************
 *	Counter Register - Bank 0 - Offset 6
 ****************************************************************************
 */
#define LAN91C96_ECR_SNGL_COL     (0xFU << 0)
#define LAN91C96_ECR_MULT_COL     (0xFU << 5)
#define LAN91C96_ECR_DEF_TX       (0xFU << 8)
#define LAN91C96_ECR_EXC_DEF_TX   (0xFU << 12)

/*
 ****************************************************************************
 *	Memory Information Register - Bank 0 - OFfset 8
 ****************************************************************************
 */
#define LAN91C96_MIR_SIZE        (0x18 << 0)    /* 6144 bytes */

/*
 ****************************************************************************
 *	Memory Configuration Register - Bank 0 - Offset 10
 ****************************************************************************
 */
#define LAN91C96_MCR_MEM_RES      (0xFFU << 0)
#define LAN91C96_MCR_MEM_MULT     (0x3U << 9)
#define LAN91C96_MCR_HIGH_ID      (0x3U << 12)

#define LAN91C96_MCR_TRANSMIT_PAGES 0x6

/*
 ****************************************************************************