sparc.md

lcc,一个可变目标c语言编译器的源码

base: con13  "%0"
base: stk13  "%%fp+%0"
addr: base           "%0"
addr: ADDI4(reg,reg)  "%%%0+%%%1"
addr: ADDP4(reg,reg)  "%%%0+%%%1"
addr: ADDU4(reg,reg)  "%%%0+%%%1"
addr: stk            "%%fp+%%%0"
reg:  INDIRI1(addr)     "ldsb [%0],%%%c\n"  1
reg:  INDIRI2(addr)     "ldsh [%0],%%%c\n"  1
reg:  INDIRI4(addr)     "ld [%0],%%%c\n"    1
reg:  INDIRU1(addr)     "ldub [%0],%%%c\n"  1
reg:  INDIRU2(addr)     "lduh [%0],%%%c\n"  1
reg:  INDIRU4(addr)     "ld [%0],%%%c\n"    1
reg:  INDIRP4(addr)     "ld [%0],%%%c\n"    1
reg:  INDIRF4(addr)     "ld [%0],%%f%c\n"   1
stmt: ASGNI1(addr,reg)  "stb %%%1,[%0]\n"   1
stmt: ASGNI2(addr,reg)  "sth %%%1,[%0]\n"   1
stmt: ASGNI4(addr,reg)  "st %%%1,[%0]\n"    1
stmt: ASGNU1(addr,reg)  "stb %%%1,[%0]\n"   1
stmt: ASGNU2(addr,reg)  "sth %%%1,[%0]\n"   1
stmt: ASGNU4(addr,reg)  "st %%%1,[%0]\n"    1
stmt: ASGNP4(addr,reg)  "st %%%1,[%0]\n"    1
stmt: ASGNF4(addr,reg)  "st %%f%1,[%0]\n"   1
addrl: ADDRLP4            "%%%fp+%a"          imm(a)

reg:   INDIRF8(addrl)     "ldd [%0],%%f%c\n"  1
stmt:  ASGNF8(addrl,reg)  "std %%f%1,[%0]\n"  1
reg:  INDIRF8(base)     "# ld2 [%0],%%f%c\n"  2
stmt: ASGNF8(base,reg)  "# st2 %%f%1,[%0]\n"  2
spill:  ADDRLP4          "%a" !imm(a)

stmt: ASGNI1(spill,reg)  "set %0,%%g1\nstb %%%1,[%%fp+%%g1]\n"
stmt: ASGNI2(spill,reg)  "set %0,%%g1\nsth %%%1,[%%fp+%%g1]\n"
stmt: ASGNI4(spill,reg)  "set %0,%%g1\nst %%%1,[%%fp+%%g1]\n"
stmt: ASGNU1(spill,reg)  "set %0,%%g1\nstb %%%1,[%%fp+%%g1]\n"
stmt: ASGNU2(spill,reg)  "set %0,%%g1\nsth %%%1,[%%fp+%%g1]\n"
stmt: ASGNU4(spill,reg)  "set %0,%%g1\nst %%%1,[%%fp+%%g1]\n"
stmt: ASGNP4(spill,reg)  "set %0,%%g1\nst %%%1,[%%fp+%%g1]\n"
stmt: ASGNF4(spill,reg)  "set %0,%%g1\nst %%f%1,[%%fp+%%g1]\n"
stmt: ASGNF8(spill,reg)  "set %0,%%g1\nstd %%f%1,[%%fp+%%g1]\n"
reg: CVII4(INDIRI1(addr))  "ldsb [%0],%%%c\n"  1
reg: CVII4(INDIRI2(addr))  "ldsh [%0],%%%c\n"  1
reg: CVUU4(INDIRU1(addr))  "ldub [%0],%%%c\n"  1
reg: CVUU4(INDIRU2(addr))  "lduh [%0],%%%c\n"  1
reg: CVUI4(INDIRU1(addr))  "ldub [%0],%%%c\n"  1
reg: CVUI4(INDIRU2(addr))  "lduh [%0],%%%c\n"  1
reg: LOADI1(reg)  "mov %%%0,%%%c\n"  move(a)
reg: LOADI2(reg)  "mov %%%0,%%%c\n"  move(a)
reg: LOADI4(reg)  "mov %%%0,%%%c\n"  move(a)
reg: LOADP4(reg)  "mov %%%0,%%%c\n"  move(a)
reg: LOADU1(reg)  "mov %%%0,%%%c\n"  move(a)
reg: LOADU2(reg)  "mov %%%0,%%%c\n"  move(a)
reg: LOADU4(reg)  "mov %%%0,%%%c\n"  move(a)
reg: CNSTI1  "# reg\n"  range(a, 0, 0)
reg: CNSTI2  "# reg\n"  range(a, 0, 0)
reg: CNSTI4  "# reg\n"  range(a, 0, 0)
reg: CNSTP4  "# reg\n"  range(a, 0, 0)
reg: CNSTU1  "# reg\n"  range(a, 0, 0)
reg: CNSTU2  "# reg\n"  range(a, 0, 0)
reg: CNSTU4  "# reg\n"  range(a, 0, 0)
reg: con  "set %0,%%%c\n"  1
rc: con13  "%0"
rc: reg    "%%%0"
reg: ADDI4(reg,rc)   "add %%%0,%1,%%%c\n"  1
reg: ADDP4(reg,rc)   "add %%%0,%1,%%%c\n"  1
reg: ADDU4(reg,rc)   "add %%%0,%1,%%%c\n"  1
reg: BANDI4(reg,rc)  "and %%%0,%1,%%%c\n"  1
reg: BORI4(reg,rc)   "or %%%0,%1,%%%c\n"   1
reg: BXORI4(reg,rc)  "xor %%%0,%1,%%%c\n"  1
reg: BANDU4(reg,rc)  "and %%%0,%1,%%%c\n"  1
reg: BORU4(reg,rc)   "or %%%0,%1,%%%c\n"   1
reg: BXORU4(reg,rc)  "xor %%%0,%1,%%%c\n"  1
reg: SUBI4(reg,rc)   "sub %%%0,%1,%%%c\n"  1
reg: SUBP4(reg,rc)   "sub %%%0,%1,%%%c\n"  1
reg: SUBU4(reg,rc)   "sub %%%0,%1,%%%c\n"  1
rc5: CNSTI4  "%a"    range(a, 0, 31)
rc5: reg    "%%%0"
reg: LSHI4(reg,rc5)  "sll %%%0,%1,%%%c\n"  1
reg: LSHU4(reg,rc5)  "sll %%%0,%1,%%%c\n"  1
reg: RSHI4(reg,rc5)  "sra %%%0,%1,%%%c\n"  1
reg: RSHU4(reg,rc5)  "srl %%%0,%1,%%%c\n"  1
reg: BANDI4(reg,BCOMI4(rc))  "andn %%%0,%1,%%%c\n"  1
reg: BORI4(reg,BCOMI4(rc))   "orn %%%0,%1,%%%c\n"   1
reg: BXORI4(reg,BCOMI4(rc))  "xnor %%%0,%1,%%%c\n"  1
reg: BANDU4(reg,BCOMU4(rc))  "andn %%%0,%1,%%%c\n"  1
reg: BORU4(reg,BCOMU4(rc))   "orn %%%0,%1,%%%c\n"   1
reg: BXORU4(reg,BCOMU4(rc))  "xnor %%%0,%1,%%%c\n"  1
reg: NEGI4(reg)   "neg %%%0,%%%c\n"  1
reg: BCOMI4(reg)  "not %%%0,%%%c\n"  1
reg: BCOMU4(reg)  "not %%%0,%%%c\n"  1
reg: CVII4(reg)  "sll %%%0,8*(4-%a),%%%c; sra %%%c,8*(4-%a),%%%c\n"  2
reg: CVUU4(reg)  "sll %%%0,8*(4-%a),%%%c; srl %%%c,8*(4-%a),%%%c\n"  2
reg: CVUU4(reg)  "and %%%0,0xff,%%%c\n" (a->syms[0]->u.c.v.i == 1 ? 1 : LBURG_MAX)
reg: CVUU4(reg)  "set 0xffff,%%g1; and %%%0,%%g1,%%%c\n"  2
reg: CVUI4(reg)  "and %%%0,0xff,%%%c\n" (a->syms[0]->u.c.v.i == 1 ? 1 : LBURG_MAX)
reg: CVUI4(reg)  "set 0xffff,%%g1; and %%%0,%%g1,%%%c\n"  2
addrg: ADDRGP4        "%a"
stmt:  JUMPV(addrg)  "ba %0; nop\n"   2
stmt:  JUMPV(addr)   "jmp %0; nop\n"  2
stmt:  LABELV        "%a:\n"
stmt: EQI4(reg,rc)  "cmp %%%0,%1; be %a; nop\n"    3
stmt: EQU4(reg,rc)  "cmp %%%0,%1; be %a; nop\n"    3
stmt: GEI4(reg,rc)  "cmp %%%0,%1; bge %a; nop\n"   3
stmt: GEU4(reg,rc)  "cmp %%%0,%1; bgeu %a; nop\n"  3
stmt: GTI4(reg,rc)  "cmp %%%0,%1; bg %a; nop\n"    3
stmt: GTU4(reg,rc)  "cmp %%%0,%1; bgu %a; nop\n"   3
stmt: LEI4(reg,rc)  "cmp %%%0,%1; ble %a; nop\n"   3
stmt: LEU4(reg,rc)  "cmp %%%0,%1; bleu %a; nop\n"  3
stmt: LTI4(reg,rc)  "cmp %%%0,%1; bl %a; nop\n"    3
stmt: LTU4(reg,rc)  "cmp %%%0,%1; blu %a; nop\n"   3
stmt: NEI4(reg,rc)  "cmp %%%0,%1; bne %a; nop\n"   3
stmt: NEU4(reg,rc)  "cmp %%%0,%1; bne %a; nop\n"   3
call: ADDRGP4           "%a"
call: addr             "%0"
reg:  CALLF8(call)      "call %0; nop\n"                2
reg:  CALLF4(call)      "call %0; nop\n"                2
reg:  CALLI4(call)      "call %0; nop\n"                2
reg:  CALLP4(call)      "call %0; nop\n"                2
reg:  CALLU4(call)      "call %0; nop\n"                2
stmt: CALLV(call)       "call %0; nop\n"                2
stmt: CALLB(call,reg)   "call %0; st %%%1,[%%sp+64]; unimp %b&0xfff\n"  3

stmt: RETF8(reg)  "# ret\n"  1
stmt: RETF4(reg)  "# ret\n"  1
stmt: RETI4(reg)  "# ret\n"  1
stmt: RETU4(reg)  "# ret\n"  1
stmt: RETP4(reg)  "# ret\n"  1
stmt: ARGI4(reg)  "st %%%0,[%%sp+4*%c+68]\n"  1
stmt: ARGU4(reg)  "st %%%0,[%%sp+4*%c+68]\n"  1
stmt: ARGP4(reg)  "st %%%0,[%%sp+4*%c+68]\n"  1
stmt: ARGF4(reg)  "# ARGF4\n"  1
stmt: ARGF8(reg)  "# ARGF8\n"  1

reg: DIVI4(reg,rc)   "sra %%%0,31,%%g1; wr %%g0,%%g1,%%y; nop; nop; nop; sdiv %%%0,%1,%%%c\n"       6

reg: DIVU4(reg,rc)   "wr %%g0,%%g0,%%y; nop; nop; nop; udiv %%%0,%1,%%%c\n"       5

reg: MODI4(reg,rc)   "sra %%%0,31,%%g1; wr %%g0,%%g1,%%y; nop; nop; nop; sdiv %%%0,%1,%%g1\n; smul %%g1,%1,%%g1; sub %%%0,%%g1,%%%c\n"  8


reg: MODU4(reg,rc)   "wr %%g0,%%g0,%%y; nop; nop; nop; udiv %%%0,%1,%%g1\n; umul %%g1,%1,%%g1; sub %%%0,%%g1,%%%c\n"  7


reg: MULI4(rc,reg)   "smul %%%1,%0,%%%c\n"  1
reg: MULU4(rc,reg)   "umul %%%1,%0,%%%c\n"  1
reg: ADDF8(reg,reg)  "faddd %%f%0,%%f%1,%%f%c\n"  1
reg: ADDF4(reg,reg)  "fadds %%f%0,%%f%1,%%f%c\n"  1
reg: DIVF8(reg,reg)  "fdivd %%f%0,%%f%1,%%f%c\n"  1
reg: DIVF4(reg,reg)  "fdivs %%f%0,%%f%1,%%f%c\n"  1
reg: MULF8(reg,reg)  "fmuld %%f%0,%%f%1,%%f%c\n"  1
reg: MULF4(reg,reg)  "fmuls %%f%0,%%f%1,%%f%c\n"  1
reg: SUBF8(reg,reg)  "fsubd %%f%0,%%f%1,%%f%c\n"  1
reg: SUBF4(reg,reg)  "fsubs %%f%0,%%f%1,%%f%c\n"  1
reg: NEGF4(reg)   "fnegs %%f%0,%%f%c\n"  1
reg: LOADF4(reg)  "fmovs %%f%0,%%f%c\n"  1
reg: CVFF4(reg)   "fdtos %%f%0,%%f%c\n"  1
reg: CVFF8(reg)   "fstod %%f%0,%%f%c\n"  1
reg: CVFI4(reg)  "fstoi %%f%0,%%f0; st %%f0,[%%sp+64]; ld [%%sp+64],%%%c\n"  (a->syms[0]->u.c.v.i==4?3:LBURG_MAX)

reg: CVFI4(reg)  "fdtoi %%f%0,%%f0; st %%f0,[%%sp+64]; ld [%%sp+64],%%%c\n"  (a->syms[0]->u.c.v.i==8?3:LBURG_MAX)

reg: CVIF4(reg)  "st %%%0,[%%sp+64]; ld [%%sp+64],%%f%c; fitos %%f%c,%%f%c\n"  3

reg: CVIF8(reg)  "st %%%0,[%%sp+64]; ld [%%sp+64],%%f%c; fitod %%f%c,%%f%c\n"  3

rel: EQF8(reg,reg)  "fcmpd %%f%0,%%f%1; nop; fbe"
rel: EQF4(reg,reg)  "fcmps %%f%0,%%f%1; nop; fbe"
rel: GEF8(reg,reg)  "fcmpd %%f%0,%%f%1; nop; fbuge"
rel: GEF4(reg,reg)  "fcmps %%f%0,%%f%1; nop; fbuge"
rel: GTF8(reg,reg)  "fcmpd %%f%0,%%f%1; nop; fbug"
rel: GTF4(reg,reg)  "fcmps %%f%0,%%f%1; nop; fbug"
rel: LEF8(reg,reg)  "fcmpd %%f%0,%%f%1; nop; fbule"
rel: LEF4(reg,reg)  "fcmps %%f%0,%%f%1; nop; fbule"
rel: LTF8(reg,reg)  "fcmpd %%f%0,%%f%1; nop; fbul"
rel: LTF4(reg,reg)  "fcmps %%f%0,%%f%1; nop; fbul"
rel: NEF8(reg,reg)  "fcmpd %%f%0,%%f%1; nop; fbne"
rel: NEF4(reg,reg)  "fcmps %%f%0,%%f%1; nop; fbne"

stmt: rel  "%0 %a; nop\n"  4
reg:  LOADF8(reg)  "# LOADD\n"  2

reg:  NEGF8(reg)  "# NEGD\n"  2

stmt:  ASGNB(reg,INDIRB(reg))  "# ASGNB\n"

%%
static void progend(void){}
static void progbeg(int argc, char *argv[]) {
        int i;

        {
                union {
                        char c;
                        int i;
                } u;
                u.i = 0;
                u.c = 1;
                swap = ((int)(u.i == 1)) != IR->little_endian;
        }
        parseflags(argc, argv);
        for (i = 0; i < argc; i++)
                if (strcmp(argv[i], "-p") == 0 || strcmp(argv[i], "-pg") == 0)
                        pflag = 1;
        if (IR == &solarisIR)
                stabprefix = ".LL";
        else
                stabprefix = "L";
        for (i = 0; i < 8; i++) {
                greg[i +  0] = mkreg(stringf("g%d", i), i +  0, 1, IREG);
                greg[i +  8] = mkreg(stringf("o%d", i), i +  8, 1, IREG);
                greg[i + 16] = mkreg(stringf("l%d", i), i + 16, 1, IREG);
                greg[i + 24] = mkreg(stringf("i%d", i), i + 24, 1, IREG);
        }
        gregw = mkwildcard(greg);
        for (i = 0; i < 32; i++)
                freg[i]  = mkreg("%d", i, 1, FREG);
        for (i = 0; i < 31; i += 2)
                freg2[i] = mkreg("%d", i, 3, FREG);
        fregw = mkwildcard(freg);
        freg2w = mkwildcard(freg2);
        tmask[IREG] = 0x3fff3e00;
        vmask[IREG] = 0x3ff00000;
        tmask[FREG]  = ~(unsigned)0;
        vmask[FREG]  = 0;
}
static Symbol rmap(int opk) {
        switch (optype(opk)) {
        case I: case U: case P: case B:
                return gregw;
        case F:
                return opsize(opk) == 4 ? fregw : freg2w;
        default:
                return 0;
        }
}
static void target(Node p) {
        assert(p);
        switch (specific(p->op)) {
        case CNST+I: case CNST+U: case CNST+P:
                if (range(p, 0, 0) == 0) {
                        setreg(p, greg[0]);
                        p->x.registered = 1;
                }
                break;
        case CALL+B:
                assert(p->syms[1] && p->syms[1]->type && isfunc(p->syms[1]->type));
                p->syms[1] = intconst(freturn(p->syms[1]->type)->size);
                break;
        case CALL+F: setreg(p, opsize(p->op)==4?freg[0]:freg2[0]);     break;
        case CALL+I: case CALL+P: case CALL+U:
        case CALL+V: setreg(p, oreg[0]);      break;
        case RET+F:  rtarget(p, 0, opsize(p->op)==4?freg[0]:freg2[0]);  break;
        case RET+I: case RET+P: case RET+U:
                rtarget(p, 0, ireg[0]);
                p->kids[0]->x.registered = 1;
                break;
        case ARG+I: case ARG+P: case ARG+U:
                if (p->syms[RX]->u.c.v.i < 6) {
                        rtarget(p, 0, oreg[p->syms[RX]->u.c.v.i]);
                        p->op = LOAD+opkind(p->op);
                        setreg(p, oreg[p->syms[RX]->u.c.v.i]);
                }
                break;
        }
}
static void clobber(Node p) {
        assert(p);
        switch (specific(p->op)) {
        case CALL+B: case CALL+F: case CALL+I:
                spill(~(unsigned)3, FREG, p);
                break;
        case CALL+V:
                spill(oreg[0]->x.regnode->mask, IREG, p);
                spill(~(unsigned)3, FREG, p);
                break;
        case ARG+F:
                if (opsize(p->op) == 4 && p->syms[2]->u.c.v.i <= 6)
                        spill((1<<(p->syms[2]->u.c.v.i + 8)), IREG, p);
                else if (opsize(p->op) == 8 && p->syms[2]->u.c.v.i <= 5)
                        spill((3<<(p->syms[2]->u.c.v.i + 8))&0xff00, IREG, p);
                break;
        }
}
static int imm(Node p) {
        return range(p, -4096, 4091);
}
static void doarg(Node p) {
        assert(p && p->syms[0] && p->op != ARG+B);
        p->syms[RX] = intconst(mkactual(4,
                p->syms[0]->u.c.v.i)/4);
}
static void emit2(Node p) {
        switch (p->op) {
        case INDIR+F+sizeop(8):
                if (generic(p->kids[0]->op) != VREG) {
                        int dst = getregnum(p);
                        print("ld ["); emitasm(p->kids[0], _base_NT); print(  "],%%f%d; ", dst);
                        print("ld ["); emitasm(p->kids[0], _base_NT); print("+4],%%f%d\n", dst+1);
                }
                break;
        case ASGN+F+sizeop(8):
                if (generic(p->kids[0]->op) != VREG) {
                        int src = getregnum(p->kids[1]);
                        print("st %%f%d,[", src);   emitasm(p->kids[0], _base_NT); print("]; ");
                        print("st %%f%d,[", src+1); emitasm(p->kids[0], _base_NT); print("+4]\n");
                }
                break;
        case ARG+F+sizeop(4): {
                int n = p->syms[RX]->u.c.v.i;
                print("st %%f%d,[%%sp+4*%d+68]\n",
                        getregnum(p->x.kids[0]), n);
                if (n <= 5)
                        print("ld [%%sp+4*%d+68],%%o%d\n", n, n);
                break;
        }
        case ARG+F+sizeop(8): {
                int n = p->syms[RX]->u.c.v.i;
                int src = getregnum(p->x.kids[0]);
                print("st %%f%d,[%%sp+4*%d+68]\n", src, n);
                print("st %%f%d,[%%sp+4*%d+68]\n", src+1, n+1);
                if (n <= 5)
                        print("ld [%%sp+4*%d+68],%%o%d\n", n, n);
                if (n <= 4)
                        print("ld [%%sp+4*%d+68],%%o%d\n", n+1, n+1);
                break;
        }
        case LOAD+F+sizeop(8): {
                int dst = getregnum(p);
                int src = getregnum(p->x.kids[0]);
                print("fmovs %%f%d,%%f%d; ", src,   dst);
                print("fmovs %%f%d,%%f%d\n", src+1, dst+1);
                break;
        }
        case NEG+F+sizeop(8): {
                int dst = getregnum(p);
                int src = getregnum(p->x.kids[0]);
                print("fnegs %%f%d,%%f%d; ", src,   dst);
                print("fmovs %%f%d,%%f%d\n", src+1, dst+1);
                break;
        }
        case ASGN+B: {
                static int tmpregs[] = { 1, 2, 3 };
                dalign = salign = p->syms[1]->u.c.v.i;
                blkcopy(getregnum(p->x.kids[0]), 0,
                        getregnum(p->x.kids[1]), 0,
                        p->syms[0]->u.c.v.i, tmpregs);
                break;
        }
        }
}
static void local(Symbol p) {
        if (retstruct) {
                assert(p == retv);
                p->x.name = stringd(4*16);
                p->x.offset = 4*16;
                p->sclass = AUTO;
                retstruct = 0;
                return;
        }
        if (isscalar(p->type) && !p->addressed && !isfloat(p->type))
                p->sclass = REGISTER;
        if (askregvar(p, rmap(ttob(p->type))) == 0)
                mkauto(p);
        else if (p->scope > LOCAL)
                regvars++;
}
static void function(Symbol f, Symbol caller[], Symbol callee[], int ncalls) {
        int autos = 0, i, leaf, reg, varargs;

        if (IR == &solarisIR)
                globalend();
        regvars = 0;
        for (i = 0; callee[i]; i++)
                ;
        varargs = variadic(f->type)
                || i > 0 && strcmp(callee[i-1]->name,
                        "__builtin_va_alist") == 0;
        usedmask[0] = usedmask[1] = 0;
        freemask[0] = freemask[1] = ~(unsigned)0;
        for (i = 0; i < 8; i++)
                ireg[i]->x.regnode->vbl = NULL;
        offset = 68;
        maxargoffset = 24;
        reg = 0;
        for (i = 0; callee[i]; i++) {
                Symbol p = callee[i], q = caller[i];
                int size = roundup(q->type->size, 4);
                assert(q);
                if (isfloat(p->type) || reg >= 6) {
                        p->x.offset = q->x.offset = offset;
                        p->x.name = q->x.name = stringd(offset);
                        p->sclass = q->sclass = AUTO;
                        autos++;