x86linux.md

lcc,一个可变目标c语言编译器的源码

acon: ADDRGP4  "%a"
acon: ADDRGP8  "%a"
acon: cnst       "%0"

baseaddr: ADDRGP4       "%a"
base: reg               "(%0)"
base: ADDI4(reg,acon)   "%1(%0)"
base: ADDP4(reg,acon)   "%1(%0)"
base: ADDU4(reg,acon)   "%1(%0)"
base: ADDRFP4           "%a(%%ebp)"
base: ADDRLP4           "%a(%%ebp)"

index: reg              "%0"
index: LSHI4(reg,con1)  "%0,2"
index: LSHI4(reg,con2)  "%0,4"
index: LSHI4(reg,con3)  "%0,8"
index: LSHU4(reg,con1)  "%0,2"
index: LSHU4(reg,con2)  "%0,4"
index: LSHU4(reg,con3)  "%0,8"

con0:  CNSTI4  "1"  range(a, 0, 0)
con0:  CNSTU4  "1"  range(a, 0, 0)
con1:  CNSTI4  "1"  range(a, 1, 1)
con1:  CNSTU4  "1"  range(a, 1, 1)
con2:  CNSTI4  "2"  range(a, 2, 2)
con2:  CNSTU4  "2"  range(a, 2, 2)
con3:  CNSTI4  "3"  range(a, 3, 3)
con3:  CNSTU4  "3"  range(a, 3, 3)

addr: base                      "%0"
addr: baseaddr                  "%0"
addr: ADDI4(index,baseaddr)     "%1(,%0)"
addr: ADDP4(index,baseaddr)     "%1(,%0)"
addr: ADDU4(index,baseaddr)     "%1(,%0)"

addr: ADDI4(reg,baseaddr)       "%1(%0)"
addr: ADDP4(reg,baseaddr)       "%1(%0)"
addr: ADDU4(reg,baseaddr)       "%1(%0)"

addr: ADDI4(index,reg)          "(%1,%0)"
addr: ADDP4(index,reg)          "(%1,%0)"
addr: ADDU4(index,reg)          "(%1,%0)"

addr: index  "(,%0)"

mem1: INDIRI1(addr)  "%0"
mem1: INDIRU1(addr)  "%0"
mem2: INDIRI2(addr)  "%0"
mem2: INDIRU2(addr)  "%0"
mem4: INDIRI4(addr)  "%0"
mem4: INDIRU4(addr)  "%0"
mem4: INDIRP4(addr)  "%0"

rc: reg         "%0"
rc: con         "%0"

mr: reg         "%0"
mr: mem4        "%0"

mr1: reg        "%0"
mr1: mem1       "%0"

mr2: reg        "%0"
mr2: mem2       "%0"

mrc: mem4       "%0"  1
mrc: mem1       "%0"  1
mrc: mem2       "%0"  1
mrc: rc         "%0"

reg: addr       "leal %0,%c\n"  1
reg: mr         "movl %0,%c\n"  1
reg: mr1        "movb %0,%c\n"  1
reg: mr2        "movw %0,%c\n"  1
reg: con        "mov %0,%c\n"  1

reg: LOADI1(reg)        "# move\n"  1
reg: LOADI2(reg)        "# move\n"  1
reg: LOADI4(reg)        "# move\n"  move(a)
reg: LOADU1(reg)        "# move\n"  1
reg: LOADU2(reg)        "# move\n"  1
reg: LOADU4(reg)        "# move\n"  move(a)
reg: LOADP4(reg)        "# move\n"  move(a)
reg: ADDI4(reg,mrc)     "?movl %0,%c\naddl %1,%c\n"  1
reg: ADDP4(reg,mrc)     "?movl %0,%c\naddl %1,%c\n"  1
reg: ADDU4(reg,mrc)     "?movl %0,%c\naddl %1,%c\n"  1
reg: SUBI4(reg,mrc)     "?movl %0,%c\nsubl %1,%c\n"  1
reg: SUBP4(reg,mrc)     "?movl %0,%c\nsubl %1,%c\n"  1
reg: SUBU4(reg,mrc)     "?movl %0,%c\nsubl %1,%c\n"  1
reg: BANDI4(reg,mrc)    "?movl %0,%c\nandl %1,%c\n"  1
reg: BORI4(reg,mrc)     "?movl %0,%c\norl %1,%c\n"   1
reg: BXORI4(reg,mrc)    "?movl %0,%c\nxorl %1,%c\n"  1
reg: BANDU4(reg,mrc)    "?movl %0,%c\nandl %1,%c\n"  1
reg: BORU4(reg,mrc)     "?movl %0,%c\norl %1,%c\n"   1
reg: BXORU4(reg,mrc)    "?movl %0,%c\nxorl %1,%c\n"  1

stmt: ASGNI4(addr,ADDI4(mem4,con1))     "incl %1\n"  memop(a)
stmt: ASGNI4(addr,ADDU4(mem4,con1))     "incl %1\n"  memop(a)
stmt: ASGNP4(addr,ADDP4(mem4,con1))     "incl %1\n"  memop(a)
stmt: ASGNI4(addr,SUBI4(mem4,con1))     "decl %1\n"  memop(a)
stmt: ASGNI4(addr,SUBU4(mem4,con1))     "decl %1\n"  memop(a)
stmt: ASGNP4(addr,SUBP4(mem4,con1))     "decl %1\n"  memop(a)
stmt: ASGNI4(addr,ADDI4(mem4,rc))       "addl %2,%1\n"  memop(a)
stmt: ASGNI4(addr,SUBI4(mem4,rc))       "subl %2,%1\n"  memop(a)
stmt: ASGNU4(addr,ADDU4(mem4,rc))       "addl %2,%1\n"  memop(a)
stmt: ASGNU4(addr,SUBU4(mem4,rc))       "subl %2,%1\n"  memop(a)

stmt: ASGNI4(addr,BANDI4(mem4,rc))      "andl %2,%1\n"  memop(a)
stmt: ASGNI4(addr,BORI4(mem4,rc))       "orl %2,%1\n"   memop(a)
stmt: ASGNI4(addr,BXORI4(mem4,rc))      "xorl %2,%1\n"  memop(a)
stmt: ASGNU4(addr,BANDU4(mem4,rc))      "andl %2,%1\n"  memop(a)
stmt: ASGNU4(addr,BORU4(mem4,rc))       "orl %2,%1\n"   memop(a)
stmt: ASGNU4(addr,BXORU4(mem4,rc))      "xorl %2,%1\n"  memop(a)
reg: BCOMI4(reg)        "?movl %0,%c\nnotl %c\n"  2
reg: BCOMU4(reg)        "?movl %0,%c\nnotl %c\n"  2
reg: NEGI4(reg)         "?movl %0,%c\nnegl %c\n"  2

stmt: ASGNI4(addr,BCOMI4(mem4)) "notl %1\n"  memop(a)
stmt: ASGNU4(addr,BCOMU4(mem4)) "notl %1\n"  memop(a)
stmt: ASGNI4(addr,NEGI4(mem4))  "negl %1\n"  memop(a)
reg: LSHI4(reg,rc5)     "?movl %0,%c\nsall %1,%c\n"  2
reg: LSHU4(reg,rc5)     "?movl %0,%c\nshll %1,%c\n"  2
reg: RSHI4(reg,rc5)     "?movl %0,%c\nsarl %1,%c\n"  2
reg: RSHU4(reg,rc5)     "?movl %0,%c\nshrl %1,%c\n"  2

stmt: ASGNI4(addr,LSHI4(mem4,rc5))      "sall %2,%1\n"  memop(a)
stmt: ASGNI4(addr,LSHU4(mem4,rc5))      "shll %2,%1\n"  memop(a)
stmt: ASGNI4(addr,RSHI4(mem4,rc5))      "sarl %2,%1\n"  memop(a)
stmt: ASGNI4(addr,RSHU4(mem4,rc5))      "shrl %2,%1\n"  memop(a)

rc5: CNSTI4     "$%a"  range(a, 0, 31)
rc5: reg        "%%cl"
reg: MULI4(reg,mrc)     "?movl %0,%c\nimull %1,%c\n"  14
reg: MULI4(con,mr)      "imul %0,%1,%c\n"  13
reg: MULU4(reg,mr)      "mull %1\n"  13
reg: DIVU4(reg,reg)     "xorl %%edx,%%edx\ndivl %1\n"
reg: MODU4(reg,reg)     "xorl %%edx,%%edx\ndivl %1\n"
reg: DIVI4(reg,reg)     "cdq\nidivl %1\n"
reg: MODI4(reg,reg)     "cdq\nidivl %1\n"
reg: CVPU4(reg)         "movl %0,%c\n"  move(a)
reg: CVUP4(reg)         "movl %0,%c\n"  move(a)
reg: CVII4(INDIRI1(addr))       "movsbl %0,%c\n"  3
reg: CVII4(INDIRI2(addr))       "movswl %0,%c\n"  3
reg: CVUU4(INDIRU1(addr))       "movzbl %0,%c\n"  3
reg: CVUU4(INDIRU2(addr))       "movzwl %0,%c\n"  3
reg: CVII4(reg) "# extend\n"  3
reg: CVIU4(reg) "# extend\n"  3
reg: CVUI4(reg) "# extend\n"  3
reg: CVUU4(reg) "# extend\n"  3

reg: CVII1(reg) "# truncate\n"  1
reg: CVII2(reg) "# truncate\n"  1
reg: CVUU1(reg) "# truncate\n"  1
reg: CVUU2(reg) "# truncate\n"  1

mrca: mem4      "%0"
mrca: rc        "%0"
mrca: ADDRGP4   "$%a"
mrca: ADDRGP8   "$%a"

stmt: ASGNI1(addr,rc)           "movb %1,%0\n"   1
stmt: ASGNI2(addr,rc)           "movw %1,%0\n"   1
stmt: ASGNI4(addr,rc)           "movl %1,%0\n"   1
stmt: ASGNU1(addr,rc)           "movb %1,%0\n"   1
stmt: ASGNU2(addr,rc)           "movw %1,%0\n"   1
stmt: ASGNU4(addr,rc)           "movl %1,%0\n"   1
stmt: ASGNP4(addr,rc)           "movl %1,%0\n"   1
stmt: ARGI4(mrca)               "pushl %0\n"  1
stmt: ARGU4(mrca)               "pushl %0\n"  1
stmt: ARGP4(mrca)               "pushl %0\n"  1
stmt: ASGNB(reg,INDIRB(reg))    "movl $%a,%%ecx\nrep\nmovsb\n"
stmt: ARGB(INDIRB(reg))         "# ARGB\n"

memf: INDIRF8(addr)         "l %0"
memf: INDIRF4(addr)         "s %0"
memf: CVFF8(INDIRF4(addr))  "s %0"
memf: CVFF4(INDIRF8(addr))  "l %0"

freg: memf      "fld%0\n"  3

stmt: ASGNF8(addr,freg)         "fstpl %0\n"  7
stmt: ASGNF4(addr,freg)         "fstps %0\n"  7
stmt: ASGNF4(addr,CVFF4(freg))  "fstps %0\n"  7

stmt: ARGF8(freg)       "subl $8,%%esp\nfstpl (%%esp)\n"
stmt: ARGF4(freg)       "subl $4,%%esp\nfstps (%%esp)\n"
freg: NEGF8(freg)       "fchs\n"
freg: NEGF4(freg)       "fchs\n"

flt: memf       "%0"
flt: freg       "p %%st,%%st(1)"
flt2: memf      "%0"
flt2: freg      "rp %%st,%%st(1)"

freg: ADDF4(freg,flt)   "fadd%1\n"
freg: ADDF8(freg,flt)   "fadd%1\n"

freg: DIVF4(freg,flt2)  "fdiv%1\n"
freg: DIVF8(freg,flt2)  "fdiv%1\n"

freg: MULF4(freg,flt)   "fmul%1\n"
freg: MULF8(freg,flt)   "fmul%1\n"

freg: SUBF4(freg,flt2)  "fsub%1\n"
freg: SUBF8(freg,flt2)  "fsub%1\n"

freg: CVFF8(freg)  "# CVFF8\n"
freg: CVFF4(freg)  "sub $4,%%esp\nfstps (%%esp)\nflds (%%esp)\naddl $4,%%esp\n"  12

reg: CVFI4(freg)  "subl $8,%%esp\nfnstcw 4(%%esp)\nmovl 4(%%esp),%%edx\nmovb $12,%%dh\nmovl %%edx,0(%%esp)\nfldcw 0(%%esp)\nfistpl 0(%%esp)\npopl %c\nfldcw 0(%%esp)\naddl $4,%%esp\n" 31

freg: CVIF8(INDIRI4(addr))      "fildl %0\n"  10
freg: CVIF8(reg)  "pushl %0\nfildl (%%esp)\naddl $4,%%esp\n"  12

freg: CVIF4(INDIRI4(addr))      "fildl %0\n"  10
freg: CVIF4(reg)  "pushl %0\nfildl (%%esp)\naddl $4,%%esp\n"  12

addrj: ADDRGP4  "%a"
addrj: reg      "*%0"  2
addrj: mem4     "*%0"  2

stmt: LABELV         "%a:\n"
stmt: JUMPV(addrj)   "jmp %0\n"  3
stmt: EQI4(mem4,rc)  "cmpl %1,%0\nje %a\n"   5
stmt: GEI4(mem4,rc)  "cmpl %1,%0\njge %a\n"  5
stmt: GTI4(mem4,rc)  "cmpl %1,%0\njg %a\n"   5
stmt: LEI4(mem4,rc)  "cmpl %1,%0\njle %a\n"  5
stmt: LTI4(mem4,rc)  "cmpl %1,%0\njl %a\n"   5
stmt: NEI4(mem4,rc)  "cmpl %1,%0\njne %a\n"  5
stmt: GEU4(mem4,rc)  "cmpl %1,%0\njae %a\n"  5
stmt: GTU4(mem4,rc)  "cmpl %1,%0\nja  %a\n"  5
stmt: LEU4(mem4,rc)  "cmpl %1,%0\njbe %a\n"  5
stmt: LTU4(mem4,rc)  "cmpl %1,%0\njb  %a\n"  5
stmt: EQI4(reg,mrc)  "cmpl %1,%0\nje %a\n"   4
stmt: GEI4(reg,mrc)  "cmpl %1,%0\njge %a\n"  4
stmt: GTI4(reg,mrc)  "cmpl %1,%0\njg %a\n"   4
stmt: LEI4(reg,mrc)  "cmpl %1,%0\njle %a\n"  4
stmt: LTI4(reg,mrc)  "cmpl %1,%0\njl %a\n"   4
stmt: NEI4(reg,mrc)  "cmpl %1,%0\njne %a\n"  4

stmt: EQU4(reg,mrc)  "cmpl %1,%0\nje %a\n"   4
stmt: GEU4(reg,mrc)  "cmpl %1,%0\njae %a\n"  4
stmt: GTU4(reg,mrc)  "cmpl %1,%0\nja %a\n"   4
stmt: LEU4(reg,mrc)  "cmpl %1,%0\njbe %a\n"  4
stmt: LTU4(reg,mrc)  "cmpl %1,%0\njb %a\n"   4
stmt: NEU4(reg,mrc)  "cmpl %1,%0\njne %a\n"  4

stmt: EQI4(BANDU4(mr,con),con0) "testl %1,%0\nje %a\n" 3
stmt: NEI4(BANDU4(mr,con),con0) "testl %1,%0\njne %a\n"

stmt: EQI4(BANDU4(CVII2(INDIRI2(addr)),con),con0) "testw %1,%0\nje %a\n"
stmt: NEI4(BANDU4(CVII2(INDIRI2(addr)),con),con0) "testw %1,%0\njne %a\n"
stmt: EQI4(BANDU4(CVIU2(INDIRI2(addr)),con),con0) "testw %1,%0\nje %a\n"
stmt: NEI4(BANDU4(CVIU2(INDIRI2(addr)),con),con0) "testw %1,%0\njne %a\n"
stmt: EQI4(BANDU4(CVII1(INDIRI1(addr)),con),con0) "testb %1,%0\nje %a\n"

cmpf: INDIRF8(addr)             "l %0"
cmpf: INDIRF4(addr)             "s %0"
cmpf: CVFF8(INDIRF4(addr))      "s %0"
cmpf: freg                      "p"

stmt: EQF8(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp 1f\nje %a\n1:\n"
stmt: GEF8(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\njbe %a\n"
stmt: GTF8(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\njb %a\n"
stmt: LEF8(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\njae %a\n"
stmt: LTF8(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\nja %a\n"
stmt: NEF8(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\njne %a\n"

stmt: EQF4(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp 1f\nje %a\n1:\n"
stmt: GEF4(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\njbe %a\n"
stmt: GTF4(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\njb %a\n"
stmt: LEF4(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\njae %a\n"
stmt: LTF4(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\nja %a\n"
stmt: NEF4(cmpf,freg)  "fcomp%0\nfstsw %%ax\nsahf\njp %a\njne %a\n"

freg: DIVF8(freg,CVIF8(INDIRI4(addr)))          "fidivl %1\n"
freg: DIVF8(CVIF8(INDIRI4(addr)),freg)          "fidivrl %0\n"
freg: DIVF8(freg,CVIF8(CVII2(INDIRI2(addr))))   "fidivs %1\n"
freg: DIVF8(CVIF8(CVII2(INDIRI2(addr))),freg)   "fidivrs %0\n"
freg: MULF8(freg,CVIF8(INDIRI4(addr)))          "fimull %1\n"
freg: MULF8(freg,CVIF8(CVII2(INDIRI2(addr))))   "fimuls %1\n"
freg: SUBF8(freg,CVIF8(INDIRI4(addr)))          "fisubl %1\n"
freg: SUBF8(CVIF8(INDIRI4(addr)),freg)          "fisubrl %0\n"
freg: SUBF8(freg,CVIF8(CVII2(INDIRI2(addr))))   "fisubs %1\n"
freg: SUBF8(CVIF8(CVII2(INDIRI2(addr))),freg)   "fisubrs %0\n"
freg: ADDF8(freg,CVIF8(INDIRI4(addr)))          "fiaddl %1\n"
freg: ADDF8(freg,CVIF8(CVII2(INDIRI2(addr))))   "fiadds %1\n"
freg: ADDF8(freg,CVFF8(INDIRF4(addr)))          "fdivs %1\n"
freg: SUBF8(freg,CVFF8(INDIRF4(addr)))          "fsubs %1\n"
freg: MULF8(freg,CVFF8(INDIRF4(addr)))          "fmuls %1\n"
freg: DIVF8(freg,CVFF8(INDIRF4(addr)))          "fdivs %1\n"
freg: LOADF8(memf)                              "fld%0\n"

reg:  CALLI4(addrj)  "call %0\naddl $%a,%%esp\n"        hasargs(a)
reg:  CALLU4(addrj)  "call %0\naddl $%a,%%esp\n"        hasargs(a)
reg:  CALLP4(addrj)  "call %0\naddl $%a,%%esp\n"        hasargs(a)

reg:  CALLI4(addrj)  "call %0\n"                        1
reg:  CALLU4(addrj)  "call %0\n"                        1
reg:  CALLP4(addrj)  "call %0\n"                        1

stmt: CALLV(addrj)   "call %0\naddl $%a,%%esp\n"        hasargs(a)
stmt: CALLV(addrj)   "call %0\n"                        1

freg: CALLF4(addrj)  "call %0\naddl $%a,%%esp\n"        hasargs(a)
freg: CALLF4(addrj)  "call %0\n"                        1

stmt: CALLF4(addrj)  "call %0\naddl $%a,%%esp\nfstp %%st(0)\n"  hasargs(a)
stmt: CALLF4(addrj)  "call %0\nfstp %%st(0)\n"                  1

freg: CALLF8(addrj)  "call %0\naddl $%a,%%esp\n"        hasargs(a)
freg: CALLF8(addrj)  "call %0\n"                        1

stmt: CALLF8(addrj)  "call %0\naddl $%a,%%esp\nfstp %%st(0)\n"  hasargs(a)
stmt: CALLF8(addrj)  "call %0\nfstp %%st(0)\n"                  1

stmt: RETI4(reg)  "# ret\n"
stmt: RETU4(reg)  "# ret\n"
stmt: RETP4(reg)  "# ret\n"
stmt: RETF4(freg) "# ret\n"
stmt: RETF8(freg) "# ret\n"
%%
static void progbeg(int argc, char *argv[]) {
        int i;
        extern Interface x86IR, x86linuxIR;

#define xx(f) assert(!x86linuxIR.f); x86linuxIR.f = x86IR.f
        xx(address);
        xx(local);
        xx(x.blkfetch);
        xx(x.blkstore);
        xx(x.blkloop);
        xx(x.doarg);
#undef xx
        {
                union {
                        char c;
                        int i;
                } u;
                u.i = 0;
                u.c = 1;
                swap = ((int)(u.i == 1)) != IR->little_endian;
        }
        parseflags(argc, argv);
        for (i = 0; i < argc; i++)
                if (strcmp(argv[i], "-p") == 0 || strcmp(argv[i], "-pg") == 0)
                        pflag = 1;      
        intreg[EAX]   = mkreg("%%eax", EAX, 1, IREG);
        intreg[EDX]   = mkreg("%%edx", EDX, 1, IREG);
        intreg[ECX]   = mkreg("%%ecx", ECX, 1, IREG);
        intreg[EBX]   = mkreg("%%ebx", EBX, 1, IREG);
        intreg[ESI]   = mkreg("%%esi", ESI, 1, IREG);
        intreg[EDI]   = mkreg("%%edi", EDI, 1, IREG);
        shortreg[EAX] = mkreg("%%ax", EAX, 1, IREG);
        shortreg[ECX] = mkreg("%%cx", ECX, 1, IREG);
        shortreg[EDX] = mkreg("%%dx", EDX, 1, IREG);
        shortreg[EBX] = mkreg("%%bx", EBX, 1, IREG);
        shortreg[ESI] = mkreg("%%si", ESI, 1, IREG);
        shortreg[EDI] = mkreg("%%di", EDI, 1, IREG);