cyp_hw.h

windows CE下cypress USB driver的例程

#define SX2_FLAG_FLUSH_FIFO8        0x80

#define SX2_SET_FLUSH_FIFO6(x)      (x |= 0x40)
#define SX2_FLAG_FLUSH_FIFO6        0x40

#define SX2_SET_FLUSH_FIFO4(x)      (x |= 0x20)
#define SX2_FLAG_FLUSH_FIFO4        0x20

#define SX2_SET_FLUSH_FIFO2(x)      (x |= 0x10)
#define SX2_FLAG_FLUSH_FIFO2        0x10

#define SX2_SET_PKTEND_EP8(x)       (x |= 0x08)
#define SX2_FLAG_PKTEND_EP8         0x08

#define SX2_SET_PKTEND_EP6(x)       (x |= 0x06)
#define SX2_FLAG_PKTEND_EP6         0x06

#define SX2_SET_PKTEND_EP4(x)       (x |= 0x04)
#define SX2_FLAG_PKTEND_EP4         0x04

#define SX2_SET_PKTEND_EP2(x)       (x |= 0x02)
#define SX2_FLAG_PKTEND_EP2         0x02

//USBFRAMEH/L registers
#define SX2_GET_FRAME_COUNT(high, low)  (((high & 0x07) << 8) + low)

//MICROFRAME register
#define SX2_GET_MICROFRAME_NUMBER(x)       (x & 0x07)

//FNADDR register
#define SX2_GET_HSGRANT(x)          ((x & 0x80) >> 7)
#define SX2_IS_FULL_SPEED(x)        ((x & 0x80) == 0x00)     // 12 Mbits/sec
#define SX2_IS_HIGH_SPEED(x)        (x & 0x80)               // 480 Mbits/sec

#define SX2_GET_FNADDR(x)           (x & 0x7F)

//INTENABLE register
#define SX2_GET_INTENABLE_SETUP(x)  ((x & 0x80) >> 7)
#define SX2_SET_INTENABLE_SETUP(x)  (x |= 0x80)

#define SX2_GET_INTENABLE_EP0BUF(x) ((x & 0x40) >> 6)
#define SX2_SET_INTENABLE_EP0BUF(x) (x |= 0x40)

#define SX2_GET_INTENABLE_FLAGS(x)  ((x & 0x20) >> 5)
#define SX2_SET_INTENABLE_FLAGS(x)  (x |= 0x20)

#define SX2_GET_INTENABLE_ENUMOK(x) ((x & 0x04) >> 2)
#define SX2_SET_INTENABLE_ENUMOK(x) (x |= 0x04)

#define SX2_GET_INTENABLE_BUS_ACTIVITY(x)  ((x & 0x02) >> 1)
#define SX2_SET_INTENABLE_BUS_ACTIVITY(x)  (x |= 0x02)

#define SX2_GET_INTENABLE_READY(x)  (x & 0x01)
#define SX2_SET_INTENABLE_READY(x)  (x |= 0x01)

//IRQ register
#define SX2_IS_IRQ_SETUP(x)         (x & 0x80)
#define SX2_IS_IRQ_EP0BUF(x)        (x & 0x40)
#define SX2_IS_IRQ_FLAGS(x)         (x & 0x20)
#define SX2_IS_IRQ_ENUMOK(x)        (x & 0x04)
#define SX2_IS_IRQ_BUS_ACTIVITY(x)  (x & 0x02)
#define SX2_IS_IRQ_READY(x)         (x & 0x01)

////////////////////////////////////////////////////////////////////////////////
// Set the FIFO addr pins

#define SX2_FIFO2         0x00
#define SX2_FIFO4         0x01
#define SX2_FIFO6         0x02
#define SX2_FIFO8         0x03
#define SX2_COMMAND       0x04


////////////////////////////////////////////////////////////////////////////////
// SX2 Pluse Command ID

#define SX2_PLUS_SETUP_PKT_CMD         		0x01
#define SX2_PLUS_OUT_PHASE_CMD         		0x02
#define SX2_PLUS_IN_PHASE_CMD         		0x03
#define SX2_PLUS_READ_REG_CMD         		0x04
#define SX2_PLUS_SETUP_CPLT_CMD         	0x06

#define SX2_PLUS_READ_REG_RESP_CMD         	0x40
#define SX2_PLUS_WRITE_REG_WITH_RESP_CMD    0x05
#define SX2_PLUS_WRITE_REG_CMD         		0x40
#define SX2_PLUS_WRITE_REG_RESP_CMD         0x07
#define SX2_PLUS_WRITE_DESC_CMD         	0x08
#define SX2_PLUS_IN_SHORT_PKT_EP2_CMD       0x80
#define SX2_PLUS_IN_SHORT_PKT_EP6_CMD       0xC0
#define SX2_PLUS_IN_SHORT_PKT_ACK_CMD       0x0A
#define SX2_PLUS_OUT_SHORT_PKT_EP2_RCVD_CMD 0x80
#define SX2_PLUS_OUT_SHORT_PKT_EP6_RCVD_CMD 0xC0
#define SX2_PLUS_OUT_SHORT_PKT_ACK_CMD      0x0C
#define SX2_PLUS_OUT_DATA_EP1_CMD         	0x0D
#define SX2_PLUS_OUT_DATA_EP1_WITH_PKT_CMD  0x0E
#define SX2_PLUS_IN_DATA_EP1_CMD         	0x0F
#define SX2_PLUS_IN_DATA_EP1_WITH_PKT_CMD   0x10

#define CMD_MASK							0xC0


////////////////////////////////////////////////////////////////////////////////
// Standard Chapter 9 definitions from the USB 2.0 specifications (http://www.usg.org)

// Request Codes
#define GET_STATUS      0x00
#define CLEAR_FEATURE   0x01
#define SET_FEATURE     0x03
#define SET_ADDRESS     0x05
#define GET_DESCRIPTOR  0x06
#define SET_DESCRIPTOR  0x07
#define GET_CONFIG      0x08
#define SET_CONFIG      0x09
#define GET_INTERFACE   0x0a
#define SET_INTERFACE   0x0b
#define SET_CONTROL_LINE_STATE  0x22   // Device specific request


// Descriptor Types
#define DESC_DEVICE             0x01
#define DESC_CONFIGURATION      0x02
#define DESC_STRING             0x03
#define DESC_INTERFACE          0x04
#define DESC_ENDPOINT           0x05
#define DESC_DEVICE_QUALIFIER   0x06
#define DESC_OTHER_SPEED_CONF   0x07
#define DESC_INTERFACE_POWER    0x08

#define DESC_SELF_POWERED       0x40
#define DESC_REMOTE_WAKEUP      0x20

#define DESC_ENDPOINT_OUT       0x00
#define DESC_ENDPOINT_IN        0x80

#define DESC_ENDPOINT_CONTROL   0x00
#define DESC_ENDPOINT_ISO       0x01
#define DESC_ENDPOINT_BULK      0x02
#define DESC_ENDPOINT_INT       0x03

#define SX2_IS_VENDOR_REQ(x)        ((x & 0x60) == 0x40)
#define SX2_IS_CLASS_REQ(x)         ((x & 0x60) == 0x20)
#define SX2_IS_DEVICE_REQ(x)        ((x & 0x1f) == 0)
#define SX2_IS_INTERFACE_REQ(x)     (x & 0x01)
#define SX2_IS_ENDPOINT_REQ(x)      (x & 0x02)

#define iCONF     18

#if INT_SETTING
#define HS_CFGLEN       63
#else
#define HS_CFGLEN       32
#endif
#define HS_TLEN         (HS_CFGLEN + 18)

#define FS_CFGLEN       32
#define FS_TLEN         (FS_CFGLEN + 18)

#define EP0Len                      64

#if INT_SETTING
#define HS_EP2Len                  512
#define HS_EP4Len                  512
#define HS_EP6Len                  512
#define HS_EP8Len                  512
#else
#define HS_EP2Len                  1024
#define HS_EP4Len                  512
#define HS_EP6Len                  512
#define HS_EP8Len                  512
#endif

#define FS_EP2Len                  64
#define FS_EP4Len                  64
#define FS_EP6Len                  64
#define FS_EP8Len                  64

#define ENDPOINT_HALT               0

#define SX2_MTU                     512 

// input pins
#define GPIO_SX2_RDY          GPIO_14

#define GPIO_SX2_FLAGA      GPIO_42  //BTRXD
#define GPIO_SX2_FLAGB      GPIO_43  //BTTXD
#define GPIO_SX2_FLAGC      GPIO_13
#define GPIO_SX2_INT           GPIO_9

// output pins
#define GPIO_SX2_PKTEND     GPIO_80  //nCS4
#define GPIO_SX2_WAKEUP    GPIO_1



//#define CLEAR_PKTEND(pContext) ((pContext)->pGPIORegs->GPSR_z |= GPIO_SX2_PKTEND)
//#define ASSERT_PKTEND(pContext) ((pContext)->pGPIORegs->GPCR_z |= GPIO_SX2_PKTEND)

#define ASSERT_WAKEUP(pContext) ((pContext)->pGPIORegs->GPCR_x |= GPIO_SX2_WAKEUP)

#define GPIO_PIN_IN         0
#define GPIO_PIN_OUT        1

#define HAS_DATA_FIFO_OUT(x) ((x)->pGPIORegs->GPLR_y & GPIO_SX2_FLAGB)
//#define IS_FULL_FIFO_OUT(x) (!((x)->pGPIORegs->GPLR_x & GPIO_SX2_FLAGC))

//for FIFO and Command
#define HAS_DATA_COMMAND_OUT(x) ((x)->pGPIORegs->GPLR_x & GPIO_SX2_FLAGC)
#define IS_FULL_COMMAND_IN(x) (!((x)->pGPIORegs->GPLR_x & GPIO_SX2_RDY))


//FLAGA==EP2 EF
//#define IS_FULL_FIFO_IN(x) (!((x)->pGPIORegs->GPLR_x & GPIO_SX2_FLAGC))
//#define IS_FULL_FIFO_IN(x) (((x)->pGPIORegs->GPLR_x & GPIO_SX2_FLAGA))

//#define IS_EMPTY_FIFO_IN(x) (!((x)->pGPIORegs->GPLR_y & GPIO_SX2_FLAGA))

#define IS_FULL_FIFO_IN(x) (!((x)->pGPIORegs->GPLR_y & GPIO_SX2_FLAGA))

/*
#define HAS_DATA_FIFO_OUT(x) ((x)->pGPIORegs->GPLR_y & GPIO_SX2_FLAGB)
#define IS_FULL_FIFO_OUT(x) (!((x)->pGPIORegs->GPLR_x & GPIO_SX2_FLAGC))



//#define IS_FULL_FIFO_IN(x) (!((x)->pGPIORegs->GPLR_x & GPIO_SX2_FLAGC))
#define IS_FULL_FIFO_IN(x) (((x)->pGPIORegs->GPLR_x & GPIO_SX2_FLAGA))
#define IS_EMPTY_FIFO_IN(x) (!((x)->pGPIORegs->GPLR_y & GPIO_SX2_FLAGA))
*/

#define SX2_LOW_POWER_MODE      1
#define SX2_FULL_POWER_MODE     2

#define SX2_SEND_TIMEOUT            500
#define SX2_READY_TIMEOUT           600000 //15000
#define SX2_ENUMOK_TIMEOUT          3000
#define SX2_REG_RW_TIMEOUT          2000
#define SX2_COMMIT_ACK_TIMEOUT      2000
#define SX2_DMA_INTERRUPT_TIMEOUT   2000
#define SX2_INIT_WAITTIME           7000

#define SX2_NUM_FIFO_OUT_BUFFERS    3   // triple buffered
#define SX2_MAX_FIFO_OUT_BUFSIZE    (SX2_NUM_FIFO_OUT_BUFFERS * SX2_MTU)


void SX2WriteDescriptor(PSX2_CONTEXT pContext, PBYTE pbDesc, DWORD cbDesc);
BOOL SX2ReadFifoBuf(PSX2_CONTEXT pContext, PBYTE pBuf, UINT32 *pLen);
BOOL SX2WriteFifoBuf(PSX2_CONTEXT pContext, PBYTE pBuf, ULONG *pLen);
BYTE SX2ReadRegister(PSX2_CONTEXT pContext, BYTE RegAddr);
void SX2WriteRegister(PSX2_CONTEXT pContext, BYTE RegAddr, BYTE Data);
void SX2WriteRegisterWoRsp(PSX2_CONTEXT pContext, BYTE RegAddr, BYTE Data);
void SX2ReadEP0Buf(PSX2_CONTEXT pContext, PBYTE pBuf, DWORD Len);
void SX2WriteEP0Buf(PSX2_CONTEXT pContext, PBYTE pBuf, DWORD Len);
void SX2WriteEP1INBuf(PSX2_CONTEXT pContext, PBYTE pBuf, DWORD Len);
void SX2ReadSetupPacket(PSX2_CONTEXT pContext, PUSB_DEVICE_REQUEST pUdr);
VOID SX2StallEP0(PSX2_CONTEXT pContext);
BOOL SX2Init(PSX2_CONTEXT pContext);
BOOL SX2SetPowerMode(PSX2_CONTEXT pContext, DWORD Mode);
USB_BUS_SPEED SX2CheckSpeed(PSX2_CONTEXT pContext);
DWORD SX2GetAddress(PSX2_CONTEXT pContext);
BOOL SX2ReadFifoBufPIO(PSX2_CONTEXT pContext, PBYTE pBuf, UINT32 *Len);
void SX2CommitInShortPkt(PSX2_CONTEXT pContext, WORD cbToWrite, PBYTE pbLastByte);
void SX2SendOutShortPktACK(PSX2_CONTEXT pContext);
void SX2SetupComplete(PSX2_CONTEXT pContext);
VOID SX2FlushFifo(PSX2_CONTEXT pContext,DWORD dwEndpoint);
BYTE SX2ReadUnIndexReg(PSX2_CONTEXT pContext, WORD RegAddr);

#if INT_SETTING
void SX2SendUSBInt(PSX2_CONTEXT pContext, BOOL DataAvail);
#endif




#ifdef __cplusplus
}
#endif

#endif __SER_HW_H__