📄 cyp_hw.h
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//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/**************************************************************************
** FILENAME: CYP_HW.H
**
* INTEL CORPORATION PROPRIETARY INFORMATION
* Copyright(c) 2000-2002 Intel Corporation.
* All rights reserved.
*
* This software is supplied under the terms of a license agreement or
* non-disclosure agreement with Intel Corporation and may not be copied
* or disclosed in accordance with the terms of that agreement.
*
*
** PROVENANCE: 2002 All original work. Sai Prasad
**
** PURPOSE: Structures and definitions used in CYP_HW.C
**
**************************************************************************/
#ifndef __SER_HW_H__
#define __SER_HW_H__
#ifdef __cplusplus
extern "C" {
#endif
// take care of endianness
#if (_BYTE_ORDER == _BIG_ENDIAN)
#define SX2_WORD_SWAP(x) (x)
#else /* _BYTE_ORDER == _BIG_ENDIAN */
#define SX2_WORD_SWAP(x) (HIBYTE(x) | LOBYTE(x) << 8)
#endif
//#define SELF_POWERED 1
typedef struct
{
BYTE Addr;
BYTE Value;
} SX2RegArray;
//// Max Descriptor RAM Size
#define SX2_MAX_DESCRIPTOR_LENGTH 500
#define SX2_MAX_COMMAND_LENGTH 0x20
////////////////////////////////////////////////////////////////////////////////
// Cypress SX2 registers (see CY7C68001 documentation)
typedef enum SX2_REGS_tag
{
SX2_REG_IFCONFIG = 0x01,
SX2_REG_FLAGSAB = 0x02,
SX2_REG_FLAGSCD = 0x03,
SX2_REG_POLAR = 0x04,
SX2_REG_REVID = 0x05,
SX2_REG_EP2CFG = 0x06,
SX2_REG_EP1OUTCFG = 0x07,
// SX2_REG_EP4CFG = 0x07,
SX2_REG_EP6CFG = 0x08,
SX2_REG_EP1INCFG = 0x09,
// SX2_REG_EP8CFG = 0x09,
SX2_REG_EP2PKTLENH = 0x0A,
SX2_REG_EP2PKTLENL = 0x0B,
SX2_REG_EP4PKTLENH = 0x0C,
SX2_REG_EP4PKTLENL = 0x0D,
SX2_REG_EP6PKTLENH = 0x0E,
SX2_REG_EP6PKTLENL = 0x0F,
SX2_REG_EP8PKTLENH = 0x10,
SX2_REG_EP8PKTLENL = 0x11,
SX2_REG_EP2PFH = 0x12,
SX2_REG_EP2PFL = 0x13,
SX2_REG_EP4PFH = 0x14,
SX2_REG_EP4PFL = 0x15,
SX2_REG_EP6PFH = 0x16,
SX2_REG_EP6PFL = 0x17,
SX2_REG_EP8PFH = 0x18,
SX2_REG_EP8PFL = 0x19,
SX2_REG_EP2ISOINPKTS = 0x1A,
SX2_REG_EP4ISOINPKTS = 0x1B,
SX2_REG_EP6ISOINPKTS = 0x1C,
SX2_REG_EP8ISOINPKTS = 0x1D,
SX2_REG_EP24FLAGS = 0x1E,
SX2_REG_EP68FLAGS = 0x1F,
SX2_REG_EPINPKTEND = 0x20,
SX2_REG_USBFRAMEH = 0x2A,
SX2_REG_USBFRAMEL = 0x2B,
SX2_REG_MICROFRAME = 0x2C,
SX2_REG_FNADDR = 0x2D,
SX2_REG_INTENABLE = 0x2E,
SX2_REG_IRQ = 0x2F,
SX2_REG_DESC_RAM = 0x30,
SX2_REG_EP0BUF = 0x31,
SX2_REG_SETUP = 0x32,
SX2_REG_EP0BC = 0x33
} SX2_REGS;
/*
#define EP2_CFG_DEFAULT_VALUE (0xA0) // OUT Endpoint, BULK, Double Buffering (2x1024byte)
#define EP6_CFG_DEFAULT_VALUE (0xE2) // IN Endpoint, BULK, Double Buffering
#define EP8_CFG_DEFAULT_VALUE (0xE2) // IN Endpoint, BULK
#define EP4_CFG_DEFAULT_VALUE (0x21) // Invalid Buffer Size - Won't be used,OUT -BULK,
*/
#define EP2_CFG_DEFAULT_VALUE (0xA2) // OUT Endpoint, BULK, Double Buffering (2x512byte)
#define EP6_CFG_DEFAULT_VALUE (0xE2) // IN Endpoint, BULK, Double Buffering
#define EP1IN_CFG_DEFAULT_VALUE (0xB2) // IN Endpoint, Interrupt, Double Buffering,
//D7 D6 D5 D4 D3 D2 D1 D0
//80 40 20 10 8 4 2 1
////////////////////////////////////////////////////////////////////////////////
// Macros to get and set flags in Cypress registers (see CY7C68001 documentation)
// IFCONFIG register
#define SX2_IFCLKSRC(x) (x & 0x80)
#define SX2_3048MHZ(x) (x & 0x40)
#define SX2_IFCLKOE(x) (x & 0x20)
#define SX2_IFCLKPOL(x) (x & 0x10)
#define SX2_ASYNC(x) (x & 0x08)
#define SX2_STANDBY(x) (x & 0x04)
#define SX2_FLAGDCS(x) (x & 0x02)
#define SX2_DISCON(x) (x & 0x01)
// FLAGSAB/FLAGSCD registers
#define SX2_FLAGS_DEFAULT 0x0
// 1-3 are reserved
#define SX2_FLAGS_EP2_PF 0x4
#define SX2_FLAGS_EP4_PF 0x5
#define SX2_FLAGS_EP6_PF 0x6
#define SX2_FLAGS_EP8_PF 0x7
#define SX2_FLAGS_EP2_EF 0x8
#define SX2_FLAGS_EP4_EF 0x9
#define SX2_FLAGS_EP6_EF 0xA
#define SX2_FLAGS_EP8_EF 0xB
#define SX2_FLAGS_EP2_FF 0xC
#define SX2_FLAGS_EP4_FF 0xD
#define SX2_FLAGS_EP6_FF 0xE
#define SX2_FLAGS_EP8_FF 0xF
#define SX2_FLAGS_BD(x) ((x) << 4)
// POLAR register
#define SX2_WUPOL(x) (x & 0x80)
#define SX2_PKTEND(x) (x & 0x20)
#define SX2_SLOE(x) (x & 0x10)
#define SX2_SLRD(x) (x & 0x08)
#define SX2_SLWR(x) (x & 0x04)
#define SX2_EF(x) (x & 0x02)
#define SX2_FF(x) (x & 0x01)
// REVID register
#define SX2_GET_CHIP_MAJOR_REV(x) ((x & 0xF0)>>4)
#define SX2_GET_CHIP_MINOR_REV(x) (x & 0x0F)
// EPxCFG registers
#if 0 // Trying to clean up RegArray
struct SX_EP_CFG {
union {
struct {
USHORT buffering:2;
USHORT stall:1;
USHORT size:1;
USHORT type:2;
USHORT dir:1;
USHORT valid:1;
} bits;
BYTE b;
};
};
#endif
#define SX2_DISCON_BIT 0x1;
#define SX2_EP_VALID_FLAG 0x80
#define SX2_EP_INVALID_FLAG 0x00
#define SX2_EP_IS_VALID(x) ((x & 0x80) == 0x80)
#define SX2_EP_DIRECTION_OUT 0x00
#define SX2_EP_DIRECTION_IN 0x40
#define SX2_EP_GET_DIRECTION(x) ((x & 0x40) >> 6)
#define SX2_EP_SET_DIRECTION(x) ((x << 6) & 0x40)
#define SX2_EP_IS_DIRECTION_IN (x & 0x40)
#define SX2_EP_IS_DIRECTION_OUT ((x & 0x40) == 0)
#define SX2_EP_GET_TYPE(x) ((x & 0x30)>>4)
#define SX2_EP_SET_TYPE(x) ((x <<4) & 0x30)
#define SX2_EP_IS_TYPE_ISOCHRONOUS(x) (x & 0x10)
#define SX2_EP_IS_TYPE_BULK(x) (x & 0x20)
#define SX2_EP_IS_TYPE_INTERRUPT(x) (x & 0x30)
#define SX2_EP_SIZE_512_FLAG 0x00
#define SX2_EP_SIZE_1024_FLAG 0x08
#define SX2_EP_GET_SIZE(x) ((x & 0x08)>>3)
#define SX2_EP_IS_SIZE_512(x) ((x & 0x08) == 0x00)
#define SX2_EP_IS_SIZE_1024(x) (x & 0x08)
#define SX2_EP_STALL_FLAG 0x04
#define SX2_EP_NO_STALL_FLAG 0x00
#define SX2_EP_GET_STALL(x) ((x & SX2_EP_STALL_FLAG) >> 2)
#define SX2_EP_SET_STALL(x) (x |= SX2_EP_STALL_FLAG)
#define SX2_EP_CLEAR_STALL(x) (x &= ~SX2_EP_STALL_FLAG)
#define SX2_EP_BUF_DOUBLE 0x02
#define SX2_EP_GET_BUF_TYPE(x) (x & 0x03)
#define SX2_EP_IS_BUF_QUAD(x) ((x & 0x03) == 0x00)
#define SX2_EP_IS_BUF_DOUBLE(x) ((x & 0x03) == 0x02)
#define SX2_EP_IS_BUF_TRIPLE(x) ((x & 0x03) == 0x03)
// EPxPKTENH/L registers
#define SX2_GET_INFM1(x) ((x & 0x80) >> 7)
#define SX2_GET_OEP1(x) ((x & 0x40) >> 6)
#define SX2_GET_ZEROLEN(x) ((x & 0x20) >> 5)
#define SX2_SET_ZEROLEN(x) (x |= 0x20)
#define SX2_FLAG_ZEROLEN 0x20
#define SX2_GET_WORDWIDE(x) ((x & 0x10) >> 4)
#define SX2_IS_WORDWIDE_8(x) ((x & 0x10) == 0x00)
#define SX2_SET_WORDWIDE_8(x) (x &= ~0x10)
#define SX2_IS_WORDWIDE_16(x) (x & 0x10)
#define SX2_SET_WORDWIDE_16(x) (x |= 0x10)
#define SX2_FLAG_WORDWIDE 0x10
#define SX2_GET_PKTLEN(high,low) (((high & 0x07) << 8) + low)
#define SX2_SET_PKTLEN(high, low, len) {low |= (BYTE)((WORD)len & (WORD)0x00FF); high |= (BYTE)(((WORD)len & (WORD)0x700) >> 8);} //sai:check
// EPxPFH/L registers
#define SX2_FLAG_DECIS 0x80
#define SX2_GET_DECIS(x) ((x & 0x80) >> 7)
#define SX2_GET_PKTSTAT(x) ((x & 0x40) >> 6)
// saip: todo: add more defs here
// EPxISOINPKTS registers
// we are not interested in isochronous transfers. so, ignore these registers
// EP24FLAGS registers
#define SX2_GET_EP4PF(x) ((x & 0x40) >> 6)
#define SX2_GET_EP4EF(x) ((x & 0x20) >> 5)
#define SX2_GET_EP4FF(x) ((x & 0x10) >> 4)
#define SX2_GET_EP2PF(x) ((x & 0x04) >> 2)
#define SX2_GET_EP2EF(x) ((x & 0x02) >> 1)
#define SX2_GET_EP2FF(x) (x & 0x01)
// EP68FLAGS registers
#define SX2_GET_EP8PF(x) ((x & 0x40) >> 6)
#define SX2_GET_EP8EF(x) ((x & 0x20) >> 5)
#define SX2_GET_EP8FF(x) ((x & 0x10) >> 4)
#define SX2_GET_EP6PF(x) ((x & 0x04) >> 2)
#define SX2_GET_EP6EF(x) ((x & 0x02) >> 1)
#define SX2_GET_EP6FF(x) (x & 0x01)
// INPKTEND/FLUSH register
#define SX2_SET_FLUSH_FIFO8(x) (x |= 0x80)
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