reset.s

完整的Bell实验室的嵌入式文件系统TFS

/*  General notice:
 *  This code is part of a boot-monitor package developed as a generic base
 *  platform for embedded system designs.  As such, it is likely to be
 *  distributed to various projects beyond the control of the original
 *  author.  Please notify the author of any enhancements made or bugs found
 *  so that all may benefit from the changes.  In addition, notification back
 *  to the author will allow the new user to pick up changes that may have
 *  been made by other users after this version of the code was distributed.
 *
 *  Author: Ed Sutter
 *  email:  [e-mail]      (home: [e-mail])
 *  phone:  [phone]            (home: 908-889-5161)
 */

    .file "reset.s"

    .import _start
    .globl _reset
    .globl _moncomptr
    .globl _coldstart
    .globl  _warmstart
    .globl  _jmptbl
    .globl  _ipaddr
    .globl  _etheraddr

    .align  2
    .equ  StackSize,0x2000
    .comm _MonStack,StackSize
    .comm _MonStackEnd,32

    .text

_reset:
    .long _coldstart        /* 0: Power-on reset PC */
    .long _MonStackEnd      /* 1: Power-on reset SP */
    .long _coldstart        /* 2: Manual reset PC   */
    .long _MonStackEnd      /* 3: Manual reset SP   */

    /* Maintain the 0x20 offset for _moncom: */
    .long 0x00000000, 0x00000000, 0x00000000, 0x00000000

    /* Pointer to the moncom function used by application. */
_moncomptr:
    .long   _moncom

    /* Put _ipaddr on a mod16 alignment... */
    .long 0x00000000, 0x00000000, 0x00000000

/*
 * Provide space to allow a programmer to place an ascii
 * string in each of these locations as an optional point
 * of storage for MAC and/or IP address...
 */
_ipaddr:
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 
_etheraddr:
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff

    .align  2

_coldstart:
    mov.l   INITVAL,r4      /* Load r4 with INITIALIZE */

_warmstart:
    /* WaitState Control Registers (Hardware Manual pg 151): */
    mov.l   WCR1,r1
    mov.w   WCR1VAL,r2
    mov.w   r2,@r1
    mov.l   WCR2,r1
    mov.w   WCR2VAL,r2
    mov.w   r2,@r1

    /* Bus Control Registers (Hardware Manual pg 145): */
    mov.l   BCR1,r1
    mov.w   BCR1VAL,r2
    mov.w   r2,@r1
    mov.l   BCR2,r1
    mov.w   BCR2VAL,r2
    mov.w   r2,@r1

    /* DRAM Configuration Registers (Hardware Manual pg 153):  */
    mov.l   DCR,r1
    mov.w   DCRVAL,r2
    mov.w   r2,@r1
    mov.l   RTCSR,r1
    mov.w   RTCSRVAL,r2
    mov.w   r2,@r1
    mov.l   RTCNT,r1
    mov.w   RTCNTVAL,r2
    mov.w   r2,@r1
    mov.l   RTCOR,r1
    mov.w   RTCORVAL,r2
    mov.w   r2,@r1

    /* Port A I/O Configuration Registers (Hardware Manual pg 550):  */
    mov.l   PAIORH,r1
    mov.w   PAIORHVAL,r2
    mov.w   r2,@r1
    mov.l   PAIORL,r1
    mov.w   PAIORLVAL,r2
    mov.w   r2,@r1
    mov.l   PACRH,r1
    mov.w   PACRHVAL,r2
    mov.w   r2,@r1
    mov.l   PACRL1,r1
    mov.w   PACRL1VAL,r2
    mov.w   r2,@r1
    mov.l   PACRL2,r1
    mov.w   PACRL2VAL,r2
    mov.w   r2,@r1

    /* Port B I/O Configuration Registers (Hardware Manual pg 560):  */
    mov.l   PBIOR,r1
    mov.w   PBIORVAL,r2
    mov.w   r2,@r1
    mov.l   PBCR1,r1
    mov.w   PBCR1VAL,r2
    mov.w   r2,@r1
    mov.l   PBCR2,r1
    mov.w   PBCR2VAL,r2
    mov.w   r2,@r1

    /* Port D Configuration Registers (Hardware Manual pg 569): */
    mov.l   PDCRH1,r1
    mov.w   PDCRH1VAL,r2
    mov.w   r2,@r1
    mov.l   PDCRH2,r1
    mov.w   PDCRH2VAL,r2
    mov.w   r2,@r1
    mov.l   PDCRL,r1
    mov.w   PDCRLVAL,r2
    mov.w   r2,@r1

    /* Port E Configuration Registers: (Hardware Manual pg 580): */
    mov.l   PEDR,r1
    mov.w   PEDRVAL,r2
    mov.w   r2,@r1
    mov.l   PEIOR,r1
    mov.w   PEIORVAL,r2
    mov.w   r2,@r1
    mov.l   PECR1,r1
    mov.w   PECR1VAL,r2
    mov.w   r2,@r1
    mov.l   PECR2,r1
    mov.w   PECR2VAL,r2
    mov.w   r2,@r1

    /* Set PIO per hardware needs... */
    mov.l   PBDR,r1
    mov.w   PBDRVAL,r2
    mov.w   r2,@r1
    mov.l   PCDR,r1
    mov.w   PCDRVAL,r2
    mov.w   r2,@r1

    /* Load stack pointer (again). */
    mov.l   StackTag,r15

    /* Jump into C code... */
    mov.l   StartTag,r8
    jmp     @r8
    nop

    .align  2

StartTag:
    .long   _start

StackTag:
    .long _MonStackEnd  


INITVAL:
    .long   3           /* Dangerous... copied from cpu.h (INITIALIZE) */
BCR1:
    .long   0xFFFF8620
BCR2:
    .long   0xFFFF8622
WCR1:
    .long   0xFFFF8624
WCR2:
    .long   0xFFFF8626
DCR:
    .long   0xFFFF862A
RTCSR:
    .long   0xFFFF862C
RTCNT:
    .long   0xFFFF862E
RTCOR:
    .long   0xFFFF8630

PAIORH:
    .long   0xFFFF8384
PAIORL:
    .long   0xFFFF8386
PACRH:
    .long   0xFFFF8388
PACRL1:
    .long   0xFFFF838C
PACRL2:
    .long   0xFFFF838E
PBIOR:
    .long   0xFFFF8394
PBCR1:
    .long   0xFFFF8398
PBCR2:
    .long   0xFFFF839A
PDCRH1:
    .long   0xFFFF83A8
PDCRH2:
    .long   0xFFFF83AA
PDCRL:
    .long   0xFFFF83AC
PECR1:
    .long   0xFFFF83B8
PECR2:
    .long   0xFFFF83BA
PEIOR:
    .long   0xFFFF83B4

PADRH:
    .long   0xFFFF8380
PADRL:
    .long   0xFFFF8382
PBDR:
    .long   0xFFFF8390
PCDR:
    .long   0xFFFF8392
PEDR:
    .long   0xFFFF83B0

    .globl WCR1VAL

WCR1VAL:
    .short  0x0031      /* CS3=0, CS2=0, CS1=2, CS0=1 */
                        /* CS3=DSP1, CS2=DSP0, CS1=SMC, CS0=FLASH */
WCR2VAL:
    .short  0x0021      /* DRAM_DMA=2, CSX_DMA=1 */
BCR1VAL:
    .short  0x202f      /* CS0,2&3 = x16 chip selects, CS1 = 32bit */
BCR2VAL:
    .short  0xffff      /* Max IDLE for now */
DCRVAL:
    .short  0x5029      /* 32-bit DRAM  Burst enabled */
RTCSRVAL:
    .short  0x0072
RTCNTVAL:
    .short  0x0000
RTCORVAL:
    .short  0x0068
PAIORHVAL:              
    .short  0x0000      /* PA23-16 in (NA for 112 pin part) */
PAIORLVAL:
    .short  0x0000      /* PA15-0 in */
PACRHVAL:
    .short  0x5500      /* PA23-20=CTRL, PA19-16=PIO (NA for 112 pin part) */
PACRL1VAL:
    .short  0x1552      /* PA15,9=PIO, PA14-10=CTRL, PA8=IRQ2 */
PACRL2VAL:
    .short  0xac35      /* PA7-6=CTRL, PA5=IRQ1, PA4-3=PIO, PA2=IRQ0 */
PBIORVAL:
    .short  0x0000      /* All Port B I/O pins (used as PIO) are input. */
PBCR1VAL:
    .short  0x0000      /* PB9 & PB8 = PIO. */
PBCR2VAL:
    .short  0xaff5      /* PB7-6=A19-18, PB1-0=A17-A16, PB5-2=CTRL */
PDCRH1VAL:
    .short  0x5555      /* PortD=DataBus */
PDCRH2VAL:
    .short  0x5555
PDCRLVAL:
    .short  0xffff  
PECR1VAL:
    .short  0x0000      /* All of PE is PIO with PE15-11=out, PE10-0=in. */
PECR2VAL:
    .short  0x0000
PEIORVAL:
    .short  0xfcff
PBDRVAL:
    .short  0x03C3      /* PB9-6,1-0=1, PB5-2=0 */
PCDRVAL:
    .short  0xFFFF      /* PC15-0=1 (address bus) */
PEDRVAL:
    .short  0x28c3      /* 28XX: 3 LEDS on, LAN LED disabled, */
                        /* XXX3: Set INT leads on DSP inactive, */
                        /* XXCX:   */