reset.s

完整的Bell实验室的嵌入式文件系统TFS

/* 
 * reset.s: micromonitor start code
 * 
 * Perform basic initialization and then call the C function
 * "start" (in file: 'start.c') with one argument: a state
 * which is used to determine whether the monitor is 'restarting'
 * as a result of a warmstart, a coldstart, a breakpoint,
 * an untrapped exception, and so on.
 *
 * by Nick Patavalis ([e-mail])
 *    Dimitris Economou ([e-mail])
 *    Michael Manousos ([e-mail])
 *    
 * based on the BLOB start code (file: 'start.S') by
 *   Erik Mouw ([e-mail]) and
 *   Jan-Derk Bakker ([e-mail])
 *
 * $Id: reset.s,v 1.11 2001/06/21 16:42:52 decon Exp $
 */


#include "cpu.h"
#include "cpuio.h"

/********************************************************************/
    
    /* Generate ARM (not thumb) instruction set */
    .arm

/********************************************************************/
    
    /*
     * Have a separate stack for each processor mode.
     */

    /* define sizes for each mode's stack */
    .equ MonStackSz, 4096
    .equ FiqStackSz, 4096
    .equ IrqStackSz, 4096
    .equ AbtStackSz, 4096
    .equ UndStackSz, 4096
    .equ SysStackSz, APPSTACK_SIZE

    /* declare the stacks */
    .global MonStack
    .global FiqStack
    .global IrqStack
    .global AbtStack
    .global UndStack
    .global SysStack        
    
    /* allocate the stacks */
    .comm   MonStack, MonStackSz    /* for the SVC mode */
    .comm   FiqStack, FiqStackSz    /* for the FIQ mode */
    .comm   IrqStack, IrqStackSz    /* for the IRQ mode */
    .comm   AbtStack, AbtStackSz    /* for the Abort mode */
    .comm   UndStack, UndStackSz    /* for the Undef mode */
    .comm   SysStack, SysStackSz    /* for the System mode */
    /* User mode has the same stack as system mode. */

/*********************************************************************/
    
    .extern undefined_instruction
    .extern software_interrupt
    .extern abort_prefetch
    .extern abort_data
    .extern not_used
    .extern interrupt_request
    .extern fast_interrupt_request
    .extern start

    .global reset
    .global coldstart
    .global lukewarmstart
    .global warmstart
    .global ipaddr
    .global etheraddr
    .global moncomptr

/********************************************************************/
    
    .text

/********************************************************************/
        
    /*
     * Exception table
     */ 
reset:  
    b do_reset
    b undefined_instruction
    b software_interrupt
    b abort_prefetch
    b abort_data
    b not_used
    b interrupt_request
    b fast_interrupt_request

/********************************************************************/
    
    /*
     * Provide space to allow a programmer to place an ascii 
     * string in each of these locations as an optional point
     *  of storage for MAC and/or IP address...
     */ 

ipaddr:
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    
etheraddr:
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff

    @@
    @@ Pointer to the 'moncom' link function at 0x00000050
    @@
    
moncomptr:
    .long   moncom

/*********************************************************************/
    
do_reset:
    /*
     * At the end of the reset sequence, MMU, Icache, Dcache,
     * and write buffer are all disabled.
     * Also IRQs and FIQs are disabled in the processor's CPSR
     * The operating mode is SVC (supervisory mode), and the
     * PC is vectored at 0x00000000. A branch in 0x00000000
     * brings us directly here.
     */ 

coldstart:

    /*
     * Initialize interrupt controller
     */

    /* Mask off, ALL IRQs and FIQs
       0x90050004 : Interrupt controller mask register */
    mov r1, #0x90000000 /* point close to ICMR */
    add r1, r1, #0x50000    /* ... even closer */
    mov r2, #0x0        /* mask everything off */
    str r2, [r1, #0x4]  /* set mask (write to ICMR) */


    /*
     * Initialize power-manager unit
     */

        /* Field [4...0] of PPCR should be programmed during
       boot sequence for the desired full speed operation.
           The derived core clock frequency depends on the
       selected crystal oscillator (3.6864 or 3.5795MHz) */

    /* Switch the CPU to 221 MHz by writing the PPCR.
       (and assuming a 3.6864MHz Crystal Oscillator)
       Don't worry, 221 MHz is also safe for 190 MHz CPUs.
       0x90020014 : Power manager PLL control register (PPCR) */
    mov r1, #0x90000000     /* point close to PPCR */
    add r1, r1, #0x20000    /* ...even closer */
    mov r2, #0x0b       /* Select the desired clock freq */
                    /* 0x0 selects the lowest freq */
                    /* 0xb selects the highest freq */
    str r2, [r1, #0x14]     /* set frequency (write PPCR) */ 

    /*
     * Initialize memory
     */
    
#if defined USE_SA1100

    /* This part is actually for the LART. If your board needs other
       settings, you'll have to ifdef them here, although the LART
       settings work for most SA-1100 boards. */

    /* Set up the DRAM in banks 0 and 1 */
    /* MDCAS0 */
    mov r1, #0xA0000000
    mov r2,     #0xC7000000
    add r2, r2, #0x001C0000
    add r2, r2, #0x00007000
    add r2, r2, #0x0000003F
    str r2, [r1, #0x04]

    /* MDCAS1 */
    mov r2,     #0xFF000000
    add r2, r2, #0x00C70000
    add r2, r2, #0x00001C00
    add r2, r2, #0x00000071
    str r2, [r1, #0x08] 

    /* MDCAS2 */
    mov r2,     #0xFF000000
    add r2, r2, #0x00FF0000
    add r2, r2, #0x0000FF00
    add r2, r2, #0x000000FF
    str r2, [r1, #0x0C]

    /* MDCNFG */
    mov r2,     #0x03000000
    add r2, r2, #0x00340000
    add r2, r2, #0x0000B200
    add r2, r2, #0x0000002f
    str r2, [r1, #0x00]

#elif defined USE_SA1110

    /* This part probably only covers inAccess Networks' OpenRouter. 
           If your board uses other settings, you'll have to ifdef 
           them here. */

    /* Set up the SDRAM */

    mov r1, #0xA0000000 /* MDCNFG base address */

    /*
     * MDCAS00 : 0xAAAAAA9F --> trcd=6*Tcpu
     * MDCAS01 : 0xAAAAAAAA --> tccd=2*Tcpu
     * MDCAS02 : 0xAAAAAAAA --> tac=3*Tcpu
         * TCPU --> CPU clock period
         * Trcd --> RAS to CAS delay
         * Tccd --> CAS to CAS delay
         * tac  --> Delay from SDCLK rising edge to read-data 
         *          latching edge
         */
    ldr r2, =0xAAAAAA9F
    str r2, [r1, #0x04] /* MDCAS00 */
    ldr r2, =0xAAAAAAAA
    str r2, [r1, #0x08] /* MDCAS01 */       
    str r2, [r1, #0x0C] /* MDCAS02 */       

    ldr r2, =0xAAAAAA7F
    str r2, [r1, #0x20] /* MDCAS20 */   
    ldr r2, =0xAAAAAAAA
    str r2, [r1, #0x24] /* MDCAS21 */       
    str r2, [r1, #0x28] /* MDCAS22 */       

    /* [3..0]   tRASR - RAS assertion before CBR
       [15..4]  DRI - DRAM refresh interval
                    SDRAM chips have 64ms refresh time each
                    Refresh time per page (1 row x 4 banks) 64/8192 = 7812ns
                    At 110,6 MHz memory clock is 9.04159ns 
                      so the DRI should be (DRI <= 864/32 = 27 cycles) 
                            (0x2BC cycles)
           [20]     E1PIN - SDRAM clock enable pin (set by H/W)
           [21]     K1RUN - SDRAM clock run control
           [22]     K1DB2 - SDRAM clock divided by 2
           [28]     EAPD - SDRAM clock enable, auto power-down enable
           [29]     KAPD - SDRAM clock pin auto power-down enable
           [31]     SLFRSH - SDRAM self refresh control status
       
           0X00|XXXX|X011|XXXX|0000|0001|1011|0001 --> 0xXX3X01B1
    */

    ldr r2, =0x003001B1     
    str r2, [r1, #0x1C] /* MDREFR */

    /* Disable all DRAM Banks */
    ldr r2, =0x72547254
    str r2, [r1, #0x00] /* MDCNFG */

    /* Issue read requests to disabled bank to start refresh */
    ldr r1, =0xC0000000
.rept   8   
    ldr r0, [r1]
.endr

    mov r1, #0xA0000000 /* MDCNFG base address */

    /* SDRAM Configuration
       [1..0]   DE - DRAM enable bank --> 01
       [2]      DTIM - DRAM timing 1-Synchronous --> 1
       [3]      DWID - DRAM data bus width --> 0
       [6..4]   DRAC - DRAM row address bit count. Includes
                bits for bank select. --> 110 (15x9)
       [7]      CDB - Clock divide by 2 for pair 0/1
                (0 for SDRAM) --> 0
       [11..8]  tRP - RAS precharge for bank pair
                0/1 --> tRP+1 = 0010 (2 clocks)
       [13..12] tDL - CAS latency between a READ command
                and data latching --> 10 (2 memory clocks)
       [15..14] tWR - SDRAM write recovery for bank 0/1
                --> 10 (2 memory clocks)
      
       The above values are set according to the datasheet
       of the MT48LC64M16A2-75 SDRAM.

       ????|????|????|????|1010|0010|0110|0101 --> 0x????A265
    */

    ldr r2, =0x7254a265 /* Enable the bank 0 only */
    str r2, [r1, #0x00] /* MDCNFG */

        /* Setup the STATIC memories (i.e. flash for the OpenRouter) */ 

    /* Static memory control registers  
       [1..0]   RTx0 - rom type --> 00b (NonBurst ROM/Flash)
       [2]      RBW  - rom bus width --> 0b (32 bits)   
       [7..3]   RDF  - rom delay first access --> 01110b (16c)
       [12..8]      RDN  - rom delay next access --> 00111b (8c)
       [15..13]     RRR  - rom recovery time --> 010 (4c)

           MCS0 : 0100|0111|0111|0000 --> 0x4770
           MCS1 : 0100|0111|0111|0000 --> 0x4770

           Upper half-word is made identical to the lower by shifting.
    */
    
    ldr r2, =0x47704770 
    str r2, [r1, #0x10] /* MCS0 */

    ldr r2, =0x22212419 
    str r2, [r1, #0x14] /* MCS1 */

    ldr r2, =0x42196669 
    str r2, [r1, #0x2C] /* MCS2 */

    ldr r2, =0xafccafcc 
    str r2, [r1, #0x30] /* SMCNFG disable SMROM for BANKS 1/0 */

    /* Set up PCMCIA space */

    ldr r2, =0x994a994a
    str r2, [r1, #0x18]

#else
    
#error "Configuration error: CPU not defined!"
    
#endif
        
    /* 
     * Do some special setup for the selected serial port
     */
    
#if defined USE_SERIAL1

    /* 0x80020060: GPCLK/UART control register 0
       Select UART peripheral */
    ldr r0, =0x80020060
    mov r2, #1
    str r2, [r0]
    
#elif defined USE_SERIAL3
    
    /* No special setup */
    
#else
    
#error "Configuration error: serial port not defined!"
    
#endif

    mov r0, #INITIALIZE
    
    /* fall-through to 'lukewarmstart' */

/********************************************************************/
    
lukewarmstart:  
    /* Save the argument to r11 */
    mov r11, r0

    /*
     * *** DO NOT TOUCH R11 ***
     */ 

    /*
     * Set-up the stack-pointers for all operating modes
     */

    /* FIQ mode */
    mrs r0, cpsr                /* move CPSR to r0 */
    bic r0, r0, #0x1f           /* clear all mode bits */
    orr r0, r0, #0x11           /* set FIQ mode bits */
    msr CPSR_c, r0              /* move back to CPSR */
    ldr sp, =(FiqStack + FiqStackSz - 4)    /* initialize the stack ptr */
    /* IRQ mode */
    mrs r0, cpsr                /* move CPSR to r0 */
    bic r0, r0, #0x1f           /* clear all mode bits */
    orr r0, r0, #0x12           /* set IRQ mode bits */
    msr CPSR_c, r0              /* move back to CPSR */
    ldr sp, =(IrqStack + IrqStackSz - 4)    /* initialize the stack ptr */
    /* Abort mode */
    mrs r0, cpsr                /* move CPSR to r0 */
    bic r0, r0, #0x1f           /* clear all mode bits */
    orr r0, r0, #0x17           /* set Abort mode bits */
    msr CPSR_c, r0              /* move back to CPSR */
    ldr sp, =(AbtStack + AbtStackSz - 4)    /* initialize the stack ptr */
    /* Undef mode */
    mrs r0, cpsr                /* move CPSR to r0 */
    bic r0, r0, #0x1f           /* clear all mode bits */
    orr r0, r0, #0x1b           /* set Undef mode bits */
    msr CPSR_c, r0              /* move back to CPSR */
    ldr sp, =(UndStack + UndStackSz - 4)    /* initialize the stack ptr */
    /* System mode */
    mrs r0, cpsr                /* move CPSR to r0 */
    bic r0, r0, #0x1f           /* clear all mode bits */
    orr r0, r0, #0x1f           /* set System mode bits */
    msr CPSR_c, r0              /* move back to CPSR */
    ldr sp, =(SysStack + SysStackSz - 4)    /* initialize the stack ptr */
    /* 'warmstart' will take us back to SVC mode
       stack for SVC mode will also be setup in warmstart */

    mov r0, r11     /* get argument back from r11 */
    b   warmstart

    
/********************************************************************/

bailout:
    mov r0, #BAILOUT
    b   warmstart

/********************************************************************/
    
warmstart:
    /* Save the argument to r11 */
    mov r11, r0

    /*
     * *** DO NOT TOUCH R11 ***
     */ 


    /* Change (back) to SVC mode */
    mrs r0, cpsr                /* move CPSR to r0 */
    bic r0, r0, #0x1f           /* clear all mode bits */
    orr r0, r0, #0x13           /* set System mode bits */
    msr CPSR_c, r0              /* move back to CPSR */
    /* Reset the stack pointer for the SVC mode (our current mode) */
    ldr sp, =(MonStack + MonStackSz - 4)

    /*
     * Restore argument which was saved to r11 and jump to
     * the C function start().
     */ 
    
    mov r0, r11
jump_to_c:
    bl start

    /* the C code should never return */
    b reset

.align 4

/*********************************************************************/