sa-1100.h

完整的Bell实验室的嵌入式文件系统TFS

#define MCSR_ANF    0x00000100  /* Audio transmit FIFO Not Full    */
                                /* (read)                          */
#define MCSR_ANE    0x00000200  /* Audio receive FIFO Not Empty    */
                                /* (read)                          */
#define MCSR_TNF    0x00000400  /* Telecom transmit FIFO Not Full  */
                                /* (read)                          */
#define MCSR_TNE    0x00000800  /* Telecom receive FIFO Not Empty  */
                                /* (read)                          */
#define MCSR_CWC    0x00001000  /* CODEC register Write Completed  */
                                /* (read)                          */
#define MCSR_CRC    0x00002000  /* CODEC register Read Completed   */
                                /* (read)                          */
#define MCSR_ACE    0x00004000  /* Audio CODEC Enabled (read)      */
#define MCSR_TCE    0x00008000  /* Telecom CODEC Enabled (read)    */

#define MCCR1_CFS   0x00100000  /* Clock Freq. Select              */
#define MCCR1_F12MHz    (MCCR1_CFS*0)   /*  Freq. (fmc) = ~ 12 MHz         */
                                /*  (11.981 MHz)                   */
#define MCCR1_F10MHz    (MCCR1_CFS*1)   /*  Freq. (fmc) = ~ 10 MHz         */
                                /*  (9.585 MHz)                    */


/*
 * Synchronous Serial Port (SSP) control registers
 *
 * Registers
 *    Ser4SSCR0     Serial port 4 Synchronous Serial Port (SSP) Control
 *                  Register 0 (read/write).
 *    Ser4SSCR1     Serial port 4 Synchronous Serial Port (SSP) Control
 *                  Register 1 (read/write).
 *                  [Bits SPO and SP are only implemented in versions 2.0
 *                  (rev. = 8) and higher of the StrongARM SA-1100.]
 *    Ser4SSDR      Serial port 4 Synchronous Serial Port (SSP) Data
 *                  Register (read/write).
 *    Ser4SSSR      Serial port 4 Synchronous Serial Port (SSP) Status
 *                  Register (read/write).
 *
 * Clocks
 *    fxtl, Txtl    Frequency, period of the system crystal (3.6864 MHz
 *                  or 3.5795 MHz).
 *    fss, Tss      Frequency, period of the SSP communication.
 */

#define _Ser4SSCR0  0x80070060  /* Ser. port 4 SSP Control Reg. 0  */
#define _Ser4SSCR1  0x80070064  /* Ser. port 4 SSP Control Reg. 1  */
#define _Ser4SSDR   0x8007006C  /* Ser. port 4 SSP Data Reg.       */
#define _Ser4SSSR   0x80070074  /* Ser. port 4 SSP Status Reg.     */

#if LANGUAGE == C
#define Ser4SSCR0               /* Ser. port 4 SSP Control Reg. 0  */ \
                    (*((volatile Word *) io_p2v (_Ser4SSCR0)))
#define Ser4SSCR1               /* Ser. port 4 SSP Control Reg. 1  */ \
                    (*((volatile Word *) io_p2v (_Ser4SSCR1)))
#define Ser4SSDR                /* Ser. port 4 SSP Data Reg.       */ \
                    (*((volatile Word *) io_p2v (_Ser4SSDR)))
#define Ser4SSSR                /* Ser. port 4 SSP Status Reg.     */ \
                    (*((volatile Word *) io_p2v (_Ser4SSSR)))
#endif /* LANGUAGE == C */

#define SSCR0_DSS   Fld (4, 0)  /* Data Size - 1 Select [3..15]    */
#define SSCR0_DataSize(Size)        /*  Data Size Select [4..16]       */ \
                    (((Size) - 1) << FShft (SSCR0_DSS))
#define SSCR0_FRF   Fld (2, 4)  /* FRame Format                    */
#define SSCR0_Motorola              /*  Motorola Serial Peripheral     */ \
                                /*  Interface (SPI) format         */ \
                    (0 << FShft (SSCR0_FRF))
#define SSCR0_TI                /*  Texas Instruments Synchronous  */ \
                                /*  Serial format                  */ \
                    (1 << FShft (SSCR0_FRF))
#define SSCR0_National              /*  National Microwire format      */ \
                    (2 << FShft (SSCR0_FRF))
#define SSCR0_SSE   0x00000080  /* SSP Enable                      */
#define SSCR0_SCR   Fld (8, 8)  /* Serial Clock Rate divisor/2 - 1 */
                                /* fss = fxtl/(2*(SCR + 1))        */
                                /* Tss = 2*(SCR + 1)*Txtl          */
#define SSCR0_SerClkDiv(Div)        /*  Serial Clock Divisor [2..512]  */ \
                    (((Div) - 2)/2 << FShft (SSCR0_SCR))
                                /*  fss = fxtl/(2*Floor (Div/2))   */
                                /*  Tss = 2*Floor (Div/2)*Txtl     */
#define SSCR0_CeilSerClkDiv(Div)    /*  Ceil. of SerClkDiv [2..512]    */ \
                    (((Div) - 1)/2 << FShft (SSCR0_SCR))
                                /*  fss = fxtl/(2*Ceil (Div/2))    */
                                /*  Tss = 2*Ceil (Div/2)*Txtl      */

#define SSCR1_RIE   0x00000001  /* Receive FIFO 1/2-full or more   */
                                /* Interrupt Enable                */
#define SSCR1_TIE   0x00000002  /* Transmit FIFO 1/2-full or less  */
                                /* Interrupt Enable                */
#define SSCR1_LBM   0x00000004  /* Look-Back Mode                  */
#define SSCR1_SPO   0x00000008  /* Sample clock (SCLK) POlarity    */
#define SSCR1_SClkIactL (SSCR1_SPO*0)   /*  Sample Clock Inactive Low      */
#define SSCR1_SClkIactH (SSCR1_SPO*1)   /*  Sample Clock Inactive High     */
#define SSCR1_SP    0x00000010  /* Sample clock (SCLK) Phase       */
#define SSCR1_SClk1P    (SSCR1_SP*0)    /*  Sample Clock active 1 Period   */
                                /*  after frame (SFRM, 1st edge)   */
#define SSCR1_SClk1_2P  (SSCR1_SP*1)    /*  Sample Clock active 1/2 Period */
                                /*  after frame (SFRM, 1st edge)   */
#define SSCR1_ECS   0x00000020  /* External Clock Select           */
#define SSCR1_IntClk    (SSCR1_ECS*0)   /*  Internal Clock                 */
#define SSCR1_ExtClk    (SSCR1_ECS*1)   /*  External Clock (GPIO [19])     */

#define SSDR_DATA   Fld (16, 0) /* receive/transmit DATA FIFOs     */

#define SSSR_TNF    0x00000002  /* Transmit FIFO Not Full (read)   */
#define SSSR_RNE    0x00000004  /* Receive FIFO Not Empty (read)   */
#define SSSR_BSY    0x00000008  /* SSP BuSY (read)                 */
#define SSSR_TFS    0x00000010  /* Transmit FIFO 1/2-full or less  */
                                /* Service request (read)          */
#define SSSR_RFS    0x00000020  /* Receive FIFO 1/2-full or more   */
                                /* Service request (read)          */
#define SSSR_ROR    0x00000040  /* Receive FIFO Over-Run           */


/*
 * Operating System (OS) timer control registers
 *
 * Registers
 *    OSMR0         Operating System (OS) timer Match Register 0
 *                  (read/write).
 *    OSMR1         Operating System (OS) timer Match Register 1
 *                  (read/write).
 *    OSMR2         Operating System (OS) timer Match Register 2
 *                  (read/write).
 *    OSMR3         Operating System (OS) timer Match Register 3
 *                  (read/write).
 *    OSCR          Operating System (OS) timer Counter Register
 *                  (read/write).
 *    OSSR          Operating System (OS) timer Status Register
 *                  (read/write).
 *    OWER          Operating System (OS) timer Watch-dog Enable Register
 *                  (read/write).
 *    OIER          Operating System (OS) timer Interrupt Enable Register
 *                  (read/write).
 */

#define _OSMR(Nb)               /* OS timer Match Reg. [0..3]      */ \
                    (0x90000000 + (Nb)*4)
#define _OSMR0      _OSMR (0)   /* OS timer Match Reg. 0           */
#define _OSMR1      _OSMR (1)   /* OS timer Match Reg. 1           */
#define _OSMR2      _OSMR (2)   /* OS timer Match Reg. 2           */
#define _OSMR3      _OSMR (3)   /* OS timer Match Reg. 3           */
#define _OSCR       0x90000010  /* OS timer Counter Reg.           */
#define _OSSR       0x90000014  /* OS timer Status Reg.            */
#define _OWER       0x90000018  /* OS timer Watch-dog Enable Reg.  */
#define _OIER       0x9000001C  /* OS timer Interrupt Enable Reg.  */

#if LANGUAGE == C
#define OSMR                    /* OS timer Match Reg. [0..3]      */ \
                    ((volatile Word *) io_p2v (_OSMR (0)))
#define OSMR0       (OSMR [0])  /* OS timer Match Reg. 0           */
#define OSMR1       (OSMR [1])  /* OS timer Match Reg. 1           */
#define OSMR2       (OSMR [2])  /* OS timer Match Reg. 2           */
#define OSMR3       (OSMR [3])  /* OS timer Match Reg. 3           */
#define OSCR                    /* OS timer Counter Reg.           */ \
                    (*((volatile Word *) io_p2v (_OSCR)))
#define OSSR                    /* OS timer Status Reg.            */ \
                    (*((volatile Word *) io_p2v (_OSSR)))
#define OWER                    /* OS timer Watch-dog Enable Reg.  */ \
                    (*((volatile Word *) io_p2v (_OWER)))
#define OIER                    /* OS timer Interrupt Enable Reg.  */ \
                    (*((volatile Word *) io_p2v (_OIER)))
#endif /* LANGUAGE == C */

#define OSSR_M(Nb)              /* Match detected [0..3]           */ \
                    (0x00000001 << (Nb))
#define OSSR_M0     OSSR_M (0)  /* Match detected 0                */
#define OSSR_M1     OSSR_M (1)  /* Match detected 1                */
#define OSSR_M2     OSSR_M (2)  /* Match detected 2                */
#define OSSR_M3     OSSR_M (3)  /* Match detected 3                */

#define OWER_WME    0x00000001  /* Watch-dog Match Enable          */
                                /* (set only)                      */

#define OIER_E(Nb)              /* match interrupt Enable [0..3]   */ \
                    (0x00000001 << (Nb))
#define OIER_E0     OIER_E (0)  /* match interrupt Enable 0        */
#define OIER_E1     OIER_E (1)  /* match interrupt Enable 1        */
#define OIER_E2     OIER_E (2)  /* match interrupt Enable 2        */
#define OIER_E3     OIER_E (3)  /* match interrupt Enable 3        */


/*
 * Real-Time Clock (RTC) control registers
 *
 * Registers
 *    RTAR          Real-Time Clock (RTC) Alarm Register (read/write).
 *    RCNR          Real-Time Clock (RTC) CouNt Register (read/write).
 *    RTTR          Real-Time Clock (RTC) Trim Register (read/write).
 *    RTSR          Real-Time Clock (RTC) Status Register (read/write).
 *
 * Clocks
 *    frtx, Trtx    Frequency, period of the real-time clock crystal
 *                  (32.768 kHz nominal).
 *    frtc, Trtc    Frequency, period of the real-time clock counter
 *                  (1 Hz nominal).
 */

#define _RTAR       0x90010000  /* RTC Alarm Reg.                  */
#define _RCNR       0x90010004  /* RTC CouNt Reg.                  */
#define _RTTR       0x90010008  /* RTC Trim Reg.                   */
#define _RTSR       0x90010010  /* RTC Status Reg.                 */

#if LANGUAGE == C
#define RTAR                    /* RTC Alarm Reg.                  */ \
                    (*((volatile Word *) io_p2v (_RTAR)))
#define RCNR                    /* RTC CouNt Reg.                  */ \
                    (*((volatile Word *) io_p2v (_RCNR)))
#define RTTR                    /* RTC Trim Reg.                   */ \
                    (*((volatile Word *) io_p2v (_RTTR)))
#define RTSR                    /* RTC Status Reg.                 */ \
                    (*((volatile Word *) io_p2v (_RTSR)))
#endif /* LANGUAGE == C */

#define RTTR_C      Fld (16, 0) /* clock divider Count - 1         */
#define RTTR_D      Fld (10, 16)    /* trim Delete count               */
                                /* frtc = (1023*(C + 1) - D)*frtx/ */
                                /*        (1023*(C + 1)^2)         */
                                /* Trtc = (1023*(C + 1)^2)*Trtx/   */
                                /*        (1023*(C + 1) - D)       */

#define RTSR_AL     0x00000001  /* ALarm detected                  */
#define RTSR_HZ     0x00000002  /* 1 Hz clock detected             */
#define RTSR_ALE    0x00000004  /* ALarm interrupt Enable          */
#define RTSR_HZE    0x00000008  /* 1 Hz clock interrupt Enable     */


/*
 * Power Manager (PM) control registers
 *
 * Registers
 *    PMCR          Power Manager (PM) Control Register (read/write).
 *    PSSR          Power Manager (PM) Sleep Status Register (read/write).
 *    PSPR          Power Manager (PM) Scratch-Pad Register (read/write).
 *    PWER