sa-1100.h

完整的Bell实验室的嵌入式文件系统TFS

                                /* Service request (read)          */
#define SDSR0_RFS   0x00000010  /* Receive FIFO 1/3-to-2/3-full or */
                                /* more Service request (read)     */

#define SDSR1_RSY   0x00000001  /* Receiver SYnchronized (read)    */
#define SDSR1_TBY   0x00000002  /* Transmitter BusY (read)         */
#define SDSR1_RNE   0x00000004  /* Receive FIFO Not Empty (read)   */
#define SDSR1_TNF   0x00000008  /* Transmit FIFO Not Full (read)   */
#define SDSR1_RTD   0x00000010  /* Receive Transition Detected     */
#define SDSR1_EOF   0x00000020  /* receive End-Of-Frame (read)     */
#define SDSR1_CRE   0x00000040  /* receive CRC Error (read)        */
#define SDSR1_ROR   0x00000080  /* Receive FIFO Over-Run (read)    */


/*
 * High-Speed Serial to Parallel controller (HSSP) control registers
 *
 * Registers
 *    Ser2HSCR0     Serial port 2 High-Speed Serial to Parallel
 *                  controller (HSSP) Control Register 0 (read/write).
 *    Ser2HSCR1     Serial port 2 High-Speed Serial to Parallel
 *                  controller (HSSP) Control Register 1 (read/write).
 *    Ser2HSDR      Serial port 2 High-Speed Serial to Parallel
 *                  controller (HSSP) Data Register (read/write).
 *    Ser2HSSR0     Serial port 2 High-Speed Serial to Parallel
 *                  controller (HSSP) Status Register 0 (read/write).
 *    Ser2HSSR1     Serial port 2 High-Speed Serial to Parallel
 *                  controller (HSSP) Status Register 1 (read).
 *    Ser2HSCR2     Serial port 2 High-Speed Serial to Parallel
 *                  controller (HSSP) Control Register 2 (read/write).
 *                  [The HSCR2 register is only implemented in
 *                  versions 2.0 (rev. = 8) and higher of the StrongARM
 *                  SA-1100.]
 */

#define _Ser2HSCR0  0x80040060  /* Ser. port 2 HSSP Control Reg. 0 */
#define _Ser2HSCR1  0x80040064  /* Ser. port 2 HSSP Control Reg. 1 */
#define _Ser2HSDR   0x8004006C  /* Ser. port 2 HSSP Data Reg.      */
#define _Ser2HSSR0  0x80040074  /* Ser. port 2 HSSP Status Reg. 0  */
#define _Ser2HSSR1  0x80040078  /* Ser. port 2 HSSP Status Reg. 1  */
#define _Ser2HSCR2  0x90060028  /* Ser. port 2 HSSP Control Reg. 2 */

#if LANGUAGE == C
#define Ser2HSCR0               /* Ser. port 2 HSSP Control Reg. 0 */ \
                    (*((volatile Word *) io_p2v (_Ser2HSCR0)))
#define Ser2HSCR1               /* Ser. port 2 HSSP Control Reg. 1 */ \
                    (*((volatile Word *) io_p2v (_Ser2HSCR1)))
#define Ser2HSDR                /* Ser. port 2 HSSP Data Reg.      */ \
                    (*((volatile Word *) io_p2v (_Ser2HSDR)))
#define Ser2HSSR0               /* Ser. port 2 HSSP Status Reg. 0  */ \
                    (*((volatile Word *) io_p2v (_Ser2HSSR0)))
#define Ser2HSSR1               /* Ser. port 2 HSSP Status Reg. 1  */ \
                    (*((volatile Word *) io_p2v (_Ser2HSSR1)))
#define Ser2HSCR2               /* Ser. port 2 HSSP Control Reg. 2 */ \
                    (*((volatile Word *) io_p2v (_Ser2HSCR2)))
#endif /* LANGUAGE == C */

#define HSCR0_ITR   0x00000001  /* IrDA Transmission Rate          */
#define HSCR0_UART  (HSCR0_ITR*0)   /*  UART mode (115.2 kb/s if IrDA) */
#define HSCR0_HSSP  (HSCR0_ITR*1)   /*  HSSP mode (4 Mb/s)             */
#define HSCR0_LBM   0x00000002  /* Look-Back Mode                  */
#define HSCR0_TUS   0x00000004  /* Transmit FIFO Under-run Select  */
#define HSCR0_EFrmURn   (HSCR0_TUS*0)   /*  End Frame on Under-Run         */
#define HSCR0_AbortURn  (HSCR0_TUS*1)   /*  Abort on Under-Run             */
#define HSCR0_TXE   0x00000008  /* Transmit Enable                 */
#define HSCR0_RXE   0x00000010  /* Receive Enable                  */
#define HSCR0_RIE   0x00000020  /* Receive FIFO 2/5-to-3/5-full or */
                                /* more Interrupt Enable           */
#define HSCR0_TIE   0x00000040  /* Transmit FIFO 1/2-full or less  */
                                /* Interrupt Enable                */
#define HSCR0_AME   0x00000080  /* Address Match Enable            */

#define HSCR1_AMV   Fld (8, 0)  /* Address Match Value             */

#define HSDR_DATA   Fld (8, 0)  /* receive/transmit DATA FIFOs     */
#if 0                           /* Hidden receive FIFO bits        */
#define HSDR_EOF    0x00000100  /*  receive End-Of-Frame (read)    */
#define HSDR_CRE    0x00000200  /*  receive CRC Error (read)       */
#define HSDR_ROR    0x00000400  /*  Receive FIFO Over-Run (read)   */
#endif /* 0 */

#define HSSR0_EIF   0x00000001  /* Error In FIFO (read)            */
#define HSSR0_TUR   0x00000002  /* Transmit FIFO Under-Run         */
#define HSSR0_RAB   0x00000004  /* Receive ABort                   */
#define HSSR0_TFS   0x00000008  /* Transmit FIFO 1/2-full or less  */
                                /* Service request (read)          */
#define HSSR0_RFS   0x00000010  /* Receive FIFO 2/5-to-3/5-full or */
                                /* more Service request (read)     */
#define HSSR0_FRE   0x00000020  /* receive FRaming Error           */

#define HSSR1_RSY   0x00000001  /* Receiver SYnchronized (read)    */
#define HSSR1_TBY   0x00000002  /* Transmitter BusY (read)         */
#define HSSR1_RNE   0x00000004  /* Receive FIFO Not Empty (read)   */
#define HSSR1_TNF   0x00000008  /* Transmit FIFO Not Full (read)   */
#define HSSR1_EOF   0x00000010  /* receive End-Of-Frame (read)     */
#define HSSR1_CRE   0x00000020  /* receive CRC Error (read)        */
#define HSSR1_ROR   0x00000040  /* Receive FIFO Over-Run (read)    */

#define HSCR2_TXP   0x00040000  /* Transmit data Polarity (TXD_2)  */
#define HSCR2_TrDataL   (HSCR2_TXP*0)   /*  Transmit Data active Low       */
                                /*  (inverted)                     */
#define HSCR2_TrDataH   (HSCR2_TXP*1)   /*  Transmit Data active High      */
                                /*  (non-inverted)                 */
#define HSCR2_RXP   0x00080000  /* Receive data Polarity (RXD_2)   */
#define HSCR2_RcDataL   (HSCR2_RXP*0)   /*  Receive Data active Low        */
                                /*  (inverted)                     */
#define HSCR2_RcDataH   (HSCR2_RXP*1)   /*  Receive Data active High       */
                                /*  (non-inverted)                 */


/*
 * Multi-media Communications Port (MCP) control registers
 *
 * Registers
 *    Ser4MCCR0     Serial port 4 Multi-media Communications Port (MCP)
 *                  Control Register 0 (read/write).
 *    Ser4MCDR0     Serial port 4 Multi-media Communications Port (MCP)
 *                  Data Register 0 (audio, read/write).
 *    Ser4MCDR1     Serial port 4 Multi-media Communications Port (MCP)
 *                  Data Register 1 (telecom, read/write).
 *    Ser4MCDR2     Serial port 4 Multi-media Communications Port (MCP)
 *                  Data Register 2 (CODEC registers, read/write).
 *    Ser4MCSR      Serial port 4 Multi-media Communications Port (MCP)
 *                  Status Register (read/write).
 *    Ser4MCCR1     Serial port 4 Multi-media Communications Port (MCP)
 *                  Control Register 1 (read/write).
 *                  [The MCCR1 register is only implemented in
 *                  versions 2.0 (rev. = 8) and higher of the StrongARM
 *                  SA-1100.]
 *
 * Clocks
 *    fmc, Tmc      Frequency, period of the MCP communication (10 MHz,
 *                  12 MHz, or GPIO [21]).
 *    faud, Taud    Frequency, period of the audio sampling.
 *    ftcm, Ttcm    Frequency, period of the telecom sampling.
 */

#define _Ser4MCCR0  0x80060000  /* Ser. port 4 MCP Control Reg. 0  */
#define _Ser4MCDR0  0x80060008  /* Ser. port 4 MCP Data Reg. 0     */
                                /* (audio)                         */
#define _Ser4MCDR1  0x8006000C  /* Ser. port 4 MCP Data Reg. 1     */
                                /* (telecom)                       */
#define _Ser4MCDR2  0x80060010  /* Ser. port 4 MCP Data Reg. 2     */
                                /* (CODEC reg.)                    */
#define _Ser4MCSR   0x80060018  /* Ser. port 4 MCP Status Reg.     */
#define _Ser4MCCR1  0x90060030  /* Ser. port 4 MCP Control Reg. 1  */

#if LANGUAGE == C
#define Ser4MCCR0               /* Ser. port 4 MCP Control Reg. 0  */ \
                    (*((volatile Word *) io_p2v (_Ser4MCCR0)))
#define Ser4MCDR0               /* Ser. port 4 MCP Data Reg. 0     */ \
                                /* (audio)                         */ \
                    (*((volatile Word *) io_p2v (_Ser4MCDR0)))
#define Ser4MCDR1               /* Ser. port 4 MCP Data Reg. 1     */ \
                                /* (telecom)                       */ \
                    (*((volatile Word *) io_p2v (_Ser4MCDR1)))
#define Ser4MCDR2               /* Ser. port 4 MCP Data Reg. 2     */ \
                                /* (CODEC reg.)                    */ \
                    (*((volatile Word *) io_p2v (_Ser4MCDR2)))
#define Ser4MCSR                /* Ser. port 4 MCP Status Reg.     */ \
                    (*((volatile Word *) io_p2v (_Ser4MCSR)))
#define Ser4MCCR1               /* Ser. port 4 MCP Control Reg. 1  */ \
                    (*((volatile Word *) io_p2v (_Ser4MCCR1)))
#endif /* LANGUAGE == C */

#define MCCR0_ASD   Fld (7, 0)  /* Audio Sampling rate Divisor/32  */
                                /* [6..127]                        */
                                /* faud = fmc/(32*ASD)             */
                                /* Taud = 32*ASD*Tmc               */
#define MCCR0_AudSmpDiv(Div)        /*  Audio Sampling rate Divisor    */ \
                                /*  [192..4064]                    */ \
                    ((Div)/32 << FShft (MCCR0_ASD))
                                /*  faud = fmc/(32*Floor (Div/32)) */
                                /*  Taud = 32*Floor (Div/32)*Tmc   */
#define MCCR0_CeilAudSmpDiv(Div)    /*  Ceil. of AudSmpDiv [192..4064] */ \
                    (((Div) + 31)/32 << FShft (MCCR0_ASD))
                                /*  faud = fmc/(32*Ceil (Div/32))  */
                                /*  Taud = 32*Ceil (Div/32)*Tmc    */
#define MCCR0_TSD   Fld (7, 8)  /* Telecom Sampling rate           */
                                /* Divisor/32 [16..127]            */
                                /* ftcm = fmc/(32*TSD)             */
                                /* Ttcm = 32*TSD*Tmc               */
#define MCCR0_TcmSmpDiv(Div)        /*  Telecom Sampling rate Divisor  */ \
                                /*  [512..4064]                    */ \
                    ((Div)/32 << FShft (MCCR0_TSD))
                                /*  ftcm = fmc/(32*Floor (Div/32)) */
                                /*  Ttcm = 32*Floor (Div/32)*Tmc   */
#define MCCR0_CeilTcmSmpDiv(Div)    /*  Ceil. of TcmSmpDiv [512..4064] */ \
                    (((Div) + 31)/32 << FShft (MCCR0_TSD))
                                /*  ftcm = fmc/(32*Ceil (Div/32))  */
                                /*  Ttcm = 32*Ceil (Div/32)*Tmc    */
#define MCCR0_MCE   0x00010000  /* MCP Enable                      */
#define MCCR0_ECS   0x00020000  /* External Clock Select           */
#define MCCR0_IntClk    (MCCR0_ECS*0)   /*  Internal Clock (10 or 12 MHz)  */
#define MCCR0_ExtClk    (MCCR0_ECS*1)   /*  External Clock (GPIO [21])     */
#define MCCR0_ADM   0x00040000  /* A/D (audio/telecom) data        */
                                /* sampling/storing Mode           */
#define MCCR0_VldBit    (MCCR0_ADM*0)   /*  Valid Bit storing mode         */
#define MCCR0_SmpCnt    (MCCR0_ADM*1)   /*  Sampling Counter storing mode  */
#define MCCR0_TTE   0x00080000  /* Telecom Transmit FIFO 1/2-full  */
                                /* or less interrupt Enable        */
#define MCCR0_TRE   0x00100000  /* Telecom Receive FIFO 1/2-full   */
                                /* or more interrupt Enable        */
#define MCCR0_ATE   0x00200000  /* Audio Transmit FIFO 1/2-full    */
                                /* or less interrupt Enable        */
#define MCCR0_ARE   0x00400000  /* Audio Receive FIFO 1/2-full or  */
                                /* more interrupt Enable           */
#define MCCR0_LBM   0x00800000  /* Look-Back Mode                  */
#define MCCR0_ECP   Fld (2, 24) /* External Clock Prescaler - 1    */
#define MCCR0_ExtClkDiv(Div)        /*  External Clock Divisor [1..4]  */ \
                    (((Div) - 1) << FShft (MCCR0_ECP))

#define MCDR0_DATA  Fld (12, 4) /* receive/transmit audio DATA     */
                                /* FIFOs                           */

#define MCDR1_DATA  Fld (14, 2) /* receive/transmit telecom DATA   */
                                /* FIFOs                           */

                                /* receive/transmit CODEC reg.     */
                                /* FIFOs:                          */
#define MCDR2_DATA  Fld (16, 0) /*  reg. DATA                      */
#define MCDR2_RW    0x00010000  /*  reg. Read/Write (transmit)     */
#define MCDR2_Rd    (MCDR2_RW*0)    /*   reg. Read                     */
#define MCDR2_Wr    (MCDR2_RW*1)    /*   reg. Write                    */
#define MCDR2_ADD   Fld (4, 17) /*  reg. ADDress                   */

#define MCSR_ATS    0x00000001  /* Audio Transmit FIFO 1/2-full    */
                                /* or less Service request (read)  */
#define MCSR_ARS    0x00000002  /* Audio Receive FIFO 1/2-full or  */
                                /* more Service request (read)     */
#define MCSR_TTS    0x00000004  /* Telecom Transmit FIFO 1/2-full  */
                                /* or less Service request (read)  */
#define MCSR_TRS    0x00000008  /* Telecom Receive FIFO 1/2-full   */
                                /* or more Service request (read)  */
#define MCSR_ATU    0x00000010  /* Audio Transmit FIFO Under-run   */
#define MCSR_ARO    0x00000020  /* Audio Receive FIFO Over-run     */
#define MCSR_TTU    0x00000040  /* Telecom Transmit FIFO Under-run */
#define MCSR_TRO    0x00000080  /* Telecom Receive FIFO Over-run   */