📄 mcf5272.h
字号:
#define MCF5272_UART_UMR1_BC_8 (0x03)#define MCF5272_UART_UMR2_CM_NORMAL (0x00)#define MCF5272_UART_UMR2_CM_ECHO (0x40)#define MCF5272_UART_UMR2_CM_LOCAL_LOOP (0x80)#define MCF5272_UART_UMR2_CM_REMOTE_LOOP (0xC0)#define MCF5272_UART_UMR2_TXRTS (0x20)#define MCF5272_UART_UMR2_TXCTS (0x10)#define MCF5272_UART_UMR2_STOP_BITS_1 (0x07)#define MCF5272_UART_UMR2_STOP_BITS_15 (0x08)#define MCF5272_UART_UMR2_STOP_BITS_2 (0x0F)#define MCF5272_UART_UMR2_STOP_BITS(a) ((a)&0x0f) /* Stop Bit Length */#define MCF5272_UART_USR_RB (0x80)#define MCF5272_UART_USR_FE (0x40)#define MCF5272_UART_USR_PE (0x20)#define MCF5272_UART_USR_OE (0x10)#define MCF5272_UART_USR_TXEMP (0x08)#define MCF5272_UART_USR_TXRDY (0x04)#define MCF5272_UART_USR_FFULL (0x02)#define MCF5272_UART_USR_RXRDY (0x01)#define MCF5272_UART_UCSR_RCS(a) (((a)&0x0f)<<4) /* Rx Clk Select */#define MCF5272_UART_UCSR_TCS(a) ((a)&0x0f) /* Tx Clk Select */#define MCF5272_UART_UCR_NONE (0x00)#define MCF5272_UART_UCR_STOP_BREAK (0x70)#define MCF5272_UART_UCR_START_BREAK (0x60)#define MCF5272_UART_UCR_RESET_BKCHGINT (0x50)#define MCF5272_UART_UCR_RESET_ERROR (0x40)#define MCF5272_UART_UCR_RESET_TX (0x30)#define MCF5272_UART_UCR_RESET_RX (0x20)#define MCF5272_UART_UCR_RESET_MR (0x10)#define MCF5272_UART_UCR_TX_DISABLED (0x08)#define MCF5272_UART_UCR_TX_ENABLED (0x04)#define MCF5272_UART_UCR_RX_DISABLED (0x02)#define MCF5272_UART_UCR_RX_ENABLED (0x01)#define MCF5272_UART_UCCR_COS (0x10)#define MCF5272_UART_UCCR_CTS (0x01)#define MCF5272_UART_UACR_BRG (0x80)#define MCF5272_UART_UACR_CTMS_TIMER (0x60)#define MCF5272_UART_UACR_IEC (0x01)#define MCF5272_UART_UISR_COS (0x80)#define MCF5272_UART_UISR_DB (0x04)#define MCF5272_UART_UISR_RXRDY (0x02)#define MCF5272_UART_UISR_TXRDY (0x01)#define MCF5272_UART_UIMR_COS (0x80)#define MCF5272_UART_UIMR_DB (0x04)#define MCF5272_UART_UIMR_FFULL (0x02)#define MCF5272_UART_UIMR_TXRDY (0x01)/************************************************************************ SDRAM Controller Module Registers Description************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_SDRAMC_SDCCR (0x0180)#define MCF5272_SDRAMC_SDCTR (0x0184)/* Read access macros for general use */#define MCF5272_RD_SDRAMC_SDCCR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_SDRAMC_SDCCR,32)#define MCF5272_RD_SDRAMC_SDCTR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_SDRAMC_SDCTR,32)/* Write access macros for general use */#define MCF5272_WR_SDRAMC_SDCCR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_SDRAMC_SDCCR,32,DATA)#define MCF5272_WR_SDRAMC_SDCTR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_SDRAMC_SDCTR,32,DATA)/* Bit level definitions and macros */#define MCF5272_SDRAMC_SDCCR_MCAS_A7 (0x0 << 13)#define MCF5272_SDRAMC_SDCCR_MCAS_A8 (0x1 << 13)#define MCF5272_SDRAMC_SDCCR_MCAS_A9 (0x2 << 13)#define MCF5272_SDRAMC_SDCCR_MCAS_A10 (0x3 << 13)#define MCF5272_SDRAMC_SDCCR_BALOC_A19 (0x0 << 8)#define MCF5272_SDRAMC_SDCCR_BALOC_A20 (0x1 << 8)#define MCF5272_SDRAMC_SDCCR_BALOC_A21 (0x2 << 8)#define MCF5272_SDRAMC_SDCCR_BALOC_A22 (0x3 << 8)#define MCF5272_SDRAMC_SDCCR_BALOC_A23 (0x4 << 8)#define MCF5272_SDRAMC_SDCCR_BALOC_A24 (0x5 << 8)#define MCF5272_SDRAMC_SDCCR_BALOC_A25 (0x6 << 8)#define MCF5272_SDRAMC_SDCCR_BALOC_A26 (0x7 << 8)#define MCF5272_SDRAMC_SDCCR_GSL (0x00000080)#define MCF5272_SDRAMC_SDCCR_REG (0x00000010)#define MCF5272_SDRAMC_SDCCR_INV (0x00000008)#define MCF5272_SDRAMC_SDCCR_SLEEP (0x00000004)#define MCF5272_SDRAMC_SDCCR_ACT (0x00000002)#define MCF5272_SDRAMC_SDCCR_INIT (0x00000001)#define MCF5272_SDRAMC_SDCTR_RTP_66MHz (0x3D << 10)#define MCF5272_SDRAMC_SDCTR_RTP_48MHz (0x2B << 10)#define MCF5272_SDRAMC_SDCTR_RTP_33MHz (0x1D << 10)#define MCF5272_SDRAMC_SDCTR_RTP_25MHz (0x16 << 10)#define MCF5272_SDRAMC_SDCTR_RC(x) ((x & 0x3) << 8)#define MCF5272_SDRAMC_SDCTR_RP(x) ((x & 0x3) << 4)#define MCF5272_SDRAMC_SDCTR_RCD(x) ((x & 0x3) << 2)#define MCF5272_SDRAMC_SDCTR_CLT_2 (0x00000001)#define MCF5272_SDRAMC_SDCTR_CLT_3 (0x00000002)#define MCF5272_SDRAMC_SDCTR_CLT_4 (0x00000003)/************************************************************************ Timer Module Registers Description************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_TIMER0_TMR (0x0200)#define MCF5272_TIMER0_TRR (0x0204)#define MCF5272_TIMER0_TCR (0x0208)#define MCF5272_TIMER0_TCN (0x020C)#define MCF5272_TIMER0_TER (0x0210)#define MCF5272_TIMER1_TMR (0x0220)#define MCF5272_TIMER1_TRR (0x0224)#define MCF5272_TIMER1_TCR (0x0228)#define MCF5272_TIMER1_TCN (0x022C)#define MCF5272_TIMER1_TER (0x0230)#define MCF5272_TIMER2_TMR (0x0240)#define MCF5272_TIMER2_TRR (0x0244)#define MCF5272_TIMER2_TCR (0x0248)#define MCF5272_TIMER2_TCN (0x024C)#define MCF5272_TIMER2_TER (0x0250)#define MCF5272_TIMER3_TMR (0x0260)#define MCF5272_TIMER3_TRR (0x0264)#define MCF5272_TIMER3_TCR (0x0268)#define MCF5272_TIMER3_TCN (0x026C)#define MCF5272_TIMER3_TER (0x0270)#define MCF5272_TIMER_WRRR (0x0280)#define MCF5272_TIMER_WIRR (0x0284)#define MCF5272_TIMER_WCR (0x0288)#define MCF5272_TIMER_WER (0x028C)/* Read access macros for general use */#define MCF5272_RD_TIMER0_TMR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TMR,16)#define MCF5272_RD_TIMER0_TRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TRR,16)#define MCF5272_RD_TIMER0_TCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TCR,16)#define MCF5272_RD_TIMER0_TCN(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TCN,16)#define MCF5272_RD_TIMER0_TER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER0_TER,16)#define MCF5272_RD_TIMER1_TMR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TMR,16)#define MCF5272_RD_TIMER1_TRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TRR,16)#define MCF5272_RD_TIMER1_TCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TCR,16)#define MCF5272_RD_TIMER1_TCN(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TCN,16)#define MCF5272_RD_TIMER1_TER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER1_TER,16)#define MCF5272_RD_TIMER2_TMR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TMR,16)#define MCF5272_RD_TIMER2_TRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TRR,16)#define MCF5272_RD_TIMER2_TCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TCR,16)#define MCF5272_RD_TIMER2_TCN(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TCN,16)#define MCF5272_RD_TIMER2_TER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER2_TER,16)#define MCF5272_RD_TIMER3_TMR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TMR,16)#define MCF5272_RD_TIMER3_TRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TRR,16)#define MCF5272_RD_TIMER3_TCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TCR,16)#define MCF5272_RD_TIMER3_TCN(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TCN,16)#define MCF5272_RD_TIMER3_TER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER3_TER,16)#define MCF5272_RD_TIMER_TMR(IMMP,NUM) \Mcf5272_iord(IMMP,MCF5272_TIMER0_TMR + (NUM * 0x20),16)#define MCF5272_RD_TIMER_TRR(IMMP,NUM) \Mcf5272_iord(IMMP,MCF5272_TIMER0_TRR + (NUM * 0x20),16)#define MCF5272_RD_TIMER_TCR(IMMP,NUM) \Mcf5272_iord(IMMP,MCF5272_TIMER0_TCR + (NUM * 0x20),16)#define MCF5272_RD_TIMER_TCN(IMMP,NUM) \Mcf5272_iord(IMMP,MCF5272_TIMER0_TCN + (NUM * 0x20),16)#define MCF5272_RD_TIMER_TER(IMMP,NUM) \Mcf5272_iord(IMMP,MCF5272_TIMER0_TER + (NUM * 0x20),8)#define MCF5272_RD_TIMER_WRRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER_WRRR,16)#define MCF5272_RD_TIMER_WIRR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER_WIRR,16)#define MCF5272_RD_TIMER_WCR(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER_WCR,16)#define MCF5272_RD_TIMER_WER(IMMP) Mcf5272_iord(IMMP,MCF5272_TIMER_WER,16)/* Write access macros for general use */#define MCF5272_WR_TIMER0_TMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER0_TMR,16,DATA)#define MCF5272_WR_TIMER0_TRR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER0_TRR,16,DATA)#define MCF5272_WR_TIMER0_TCN(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER0_TCN,16,DATA)#define MCF5272_WR_TIMER0_TER(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER0_TER,16,DATA)#define MCF5272_WR_TIMER1_TMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER1_TMR,16,DATA)#define MCF5272_WR_TIMER1_TRR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER1_TRR,16,DATA)#define MCF5272_WR_TIMER1_TCN(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER1_TCN,16,DATA)#define MCF5272_WR_TIMER1_TER(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER1_TER,16,DATA)#define MCF5272_WR_TIMER2_TMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER2_TMR,16,DATA)#define MCF5272_WR_TIMER2_TRR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER2_TRR,16,DATA)#define MCF5272_WR_TIMER2_TCN(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER2_TCN,16,DATA)#define MCF5272_WR_TIMER2_TER(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER2_TER,16,DATA)#define MCF5272_WR_TIMER3_TMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER3_TMR,16,DATA)#define MCF5272_WR_TIMER3_TRR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER3_TRR,16,DATA)#define MCF5272_WR_TIMER3_TCN(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER3_TCN,16,DATA)#define MCF5272_WR_TIMER3_TER(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER3_TER,16,DATA)#define MCF5272_WR_TIMER_WRRR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER_WRRR,16,DATA)#define MCF5272_WR_TIMER_WIRR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER_WIRR,16,DATA)#define MCF5272_WR_TIMER_WCR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER_WCR,16,DATA)#define MCF5272_WR_TIMER_WER(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER_WER,16,DATA)#define MCF5272_WR_TIMER_TMR(IMMP,NUM,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER0_TMR + (NUM * 0x20),16,DATA)#define MCF5272_WR_TIMER_TRR(IMMP,NUM,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER0_TRR + (NUM * 0x20),16,DATA)#define MCF5272_WR_TIMER_TCN(IMMP,NUM,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER0_TCN + (NUM * 0x20),16,DATA)#define MCF5272_WR_TIMER_TER(IMMP,NUM,DATA) \ Mcf5272_iowr(IMMP,MCF5272_TIMER0_TER + (NUM * 0x20),8,DATA)/* Bit level definitions and macros */#define MCF5272_TIMER_TMR_PS(a) (((a)&0x00FF)<<8)#define MCF5272_TIMER_TMR_CE_ANY (0x00C0)#define MCF5272_TIMER_TMR_CE_RISE (0x0080)#define MCF5272_TIMER_TMR_CE_FALL (0x0040)#define MCF5272_TIMER_TMR_CE_NONE (0x0000)#define MCF5272_TIMER_TMR_OM (0x0020)#define MCF5272_TIMER_TMR_ORI (0x0010)#define MCF5272_TIMER_TMR_FRR (0x0008)#define MCF5272_TIMER_TMR_CLK_TIN (0x0006)#define MCF5272_TIMER_TMR_CLK_DIV16 (0x0004)#define MCF5272_TIMER_TMR_CLK_MSCLK (0x0002)#define MCF5272_TIMER_TMR_CLK_STOP (0x0000)#define MCF5272_TIMER_TMR_RST (0x0001)#define MCF5272_TIMER_TER_REF (0x02)#define MCF5272_TIMER_TER_CAP (0x01)/************************************************************************ PLI Module Registers Description************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_PLI_P0B1RR (0x0300)#define MCF5272_PLI_P1B1RR (0x0304)#define MCF5272_PLI_P2B1RR (0x0308)#define MCF5272_PLI_P3B1RR (0x030C)#define MCF5272_PLI_P0B2RR (0x0310)#define MCF5272_PLI_P1B2RR (0x0314)#define MCF5272_PLI_P2B2RR (0x0318)#define MCF5272_PLI_P3B2RR (0x031C)#define MCF5272_PLI_P0DRR (0x0320)#define MCF5272_PLI_P1DRR (0x0321)#define MCF5272_PLI_P2DRR (0x0322)#define MCF5272_PLI_P3DRR (0x0323)#define MCF5272_PLI_P0B1TR (0x0328)#define MCF5272_PLI_P1B1TR (0x032C)#define MCF5272_PLI_P2B1TR (0x0330)#define MCF5272_PLI_P3B1TR (0x0334)#define MCF5272_PLI_P0B2TR (0x0338)#define MCF5272_PLI_P1B2TR (0x033C)#define MCF5272_PLI_P2B2TR (0x0340)#define MCF5272_PLI_P3B2TR (0x0344)#define MCF5272_PLI_P0DTR (0x0348)#define MCF5272_PLI_P1DTR (0x0349)#define MCF5272_PLI_P2DTR (0x034A)#define MCF5272_PLI_P3DTR (0x034B)#define MCF5272_PLI_P0CR (0x0350)#define MCF5272_PLI_P1CR (0x0352)#define MCF5272_PLI_P2CR (0x0354)#define MCF5272_PLI_P3CR (0x0356)#define MCF5272_PLI_P0ICR (0x0358)#define MCF5272_PLI_P1ICR (0x035A)#define MCF5272_PLI_P2ICR (0x035C)#define MCF5272_PLI_P3ICR (0x035E)#define MCF5272_PLI_P0GMR (0x0360)#define MCF5272_PLI_P1GMR (0x0362)#define MCF5272_PLI_P2GMR (0x0364)#define MCF5272_PLI_P3GMR (0x0366)#define MCF5272_PLI_P0GMT (0x0368)#define MCF5272_PLI_P1GMT (0x036A)⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -