📄 mcf5272.h
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#define MCF5272_GPIO_DDR9_INPUT (~0x02)#define MCF5272_GPIO_DDR9_OUTPUT ( 0x02)#define MCF5272_GPIO_DDR8_INPUT (~0x01)#define MCF5272_GPIO_DDR8_OUTPUT ( 0x01)#define MCF5272_GPIO_DDR7_INPUT (~0x80)#define MCF5272_GPIO_DDR7_OUTPUT ( 0x80)#define MCF5272_GPIO_DDR6_INPUT (~0x40)#define MCF5272_GPIO_DDR6_OUTPUT ( 0x40)#define MCF5272_GPIO_DDR5_INPUT (~0x20)#define MCF5272_GPIO_DDR5_OUTPUT ( 0x20)#define MCF5272_GPIO_DDR4_INPUT (~0x10)#define MCF5272_GPIO_DDR4_OUTPUT ( 0x10)#define MCF5272_GPIO_DDR3_INPUT (~0x08)#define MCF5272_GPIO_DDR3_OUTPUT ( 0x08)#define MCF5272_GPIO_DDR2_INPUT (~0x04)#define MCF5272_GPIO_DDR2_OUTPUT ( 0x04)#define MCF5272_GPIO_DDR1_INPUT (~0x02)#define MCF5272_GPIO_DDR1_OUTPUT ( 0x02)#define MCF5272_GPIO_DDR0_INPUT (~0x01)#define MCF5272_GPIO_DDR0_OUTPUT ( 0x01)#define MCF5272_GPIO_DAT15 ( 0x80)#define MCF5272_GPIO_DAT14 ( 0x40)#define MCF5272_GPIO_DAT13 ( 0x20)#define MCF5272_GPIO_DAT12 ( 0x10)#define MCF5272_GPIO_DAT11 ( 0x08)#define MCF5272_GPIO_DAT10 ( 0x04)#define MCF5272_GPIO_DAT9 ( 0x02)#define MCF5272_GPIO_DAT8 ( 0x01)#define MCF5272_GPIO_DAT7 ( 0x80)#define MCF5272_GPIO_DAT6 ( 0x40)#define MCF5272_GPIO_DAT5 ( 0x20)#define MCF5272_GPIO_DAT4 ( 0x10)#define MCF5272_GPIO_DAT3 ( 0x08)#define MCF5272_GPIO_DAT2 ( 0x04)#define MCF5272_GPIO_DAT1 ( 0x02)#define MCF5272_GPIO_DAT0 ( 0x01)/************************************************************************ QSPI Module Registers Description************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_QSPI_QMR (0x00A0)#define MCF5272_QSPI_QDLYR (0x00A4)#define MCF5272_QSPI_QWR (0x00A8)#define MCF5272_QSPI_QIR (0x00AC)#define MCF5272_QSPI_QAR (0x00B0)#define MCF5272_QSPI_QDR (0x00B4)/* Read access macros for general use */#define MCF5272_RD_QSPI_QMR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_QSPI_QMR,16)#define MCF5272_RD_QSPI_QDLYR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_QSPI_QDLYR,16)#define MCF5272_RD_QSPI_QWR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_QSPI_QWR,16)#define MCF5272_RD_QSPI_QIR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_QSPI_QIR,16)#define MCF5272_RD_QSPI_QAR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_QSPI_QAR,16)#define MCF5272_RD_QSPI_QDR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_QSPI_QDR,16)/* Write access macros for general use */#define MCF5272_WR_QSPI_QMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_QSPI_QMR,16,DATA)#define MCF5272_WR_QSPI_QDLYR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_QSPI_QDLYR,16,DATA)#define MCF5272_WR_QSPI_QWR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_QSPI_QWR,16,DATA)#define MCF5272_WR_QSPI_QIR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_QSPI_QIR,16,DATA)#define MCF5272_WR_QSPI_QAR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_QSPI_QAR,16,DATA)#define MCF5272_WR_QSPI_QDR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_QSPI_QDR,16,DATA)/************************************************************************ PWM Module Registers Description************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_PWM_PWMCR1 (0x00C0)#define MCF5272_PWM_PWMCR2 (0x00C4)#define MCF5272_PWM_PWMCR3 (0x00C8)#define MCF5272_PWM_PWMWD1 (0x00D0)#define MCF5272_PWM_PWMWD2 (0x00D4)#define MCF5272_PWM_PWMWD3 (0x00D8)/* Read access macros for general use */#define MCF5272_RD_PWM_PWMCR1(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR1,8)#define MCF5272_RD_PWM_PWMCR2(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR2,8)#define MCF5272_RD_PWM_PWMCR3(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMCR3,8)#define MCF5272_RD_PWM_PWMWD1(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD1,8)#define MCF5272_RD_PWM_PWMWD2(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD2,8)#define MCF5272_RD_PWM_PWMWD3(IMMP) Mcf5272_iord(IMMP,MCF5272_PWM_PWMWD3,8)/* Write access macros for general use */#define MCF5272_WR_PWM_PWMCR1(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR1,8,DATA)#define MCF5272_WR_PWM_PWMCR2(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR2,8,DATA)#define MCF5272_WR_PWM_PWMCR3(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_PWM_PWMCR3,8,DATA)#define MCF5272_WR_PWM_PWMWD1(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD1,8,DATA)#define MCF5272_WR_PWM_PWMWD2(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD2,8,DATA)#define MCF5272_WR_PWM_PWMWD3(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_PWM_PWMWD3,8,DATA)/************************************************************************ DMA Module Registers Description************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_DMA_DCMR (0x00E0)#define MCF5272_DMA_DCIR (0x00E6)#define MCF5272_DMA_DBCR (0x00E8)#define MCF5272_DMA_DSAR (0x00EC)#define MCF5272_DMA_DDAR (0x00F0)/* Read access macros for general use */#define MCF5272_RD_DMA_DCMR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DCMR,32)#define MCF5272_RD_DMA_DCIR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DCIR,16)#define MCF5272_RD_DMA_DBCR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DBCR,32)#define MCF5272_RD_DMA_DSAR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DSAR,32)#define MCF5272_RD_DMA_DDAR(IMMP) Mcf5272_iord(IMMP,MCF5272_DMA_DDAR,32)/* Write access macros for general use */#define MCF5272_WR_DMA_DCMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_DMA_DCMR,32,DATA)#define MCF5272_WR_DMA_DCIR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_DMA_DCIR,16,DATA)#define MCF5272_WR_DMA_DBCR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_DMA_DBCR,32,DATA)#define MCF5272_WR_DMA_DSAR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_DMA_DSAR,32,DATA)#define MCF5272_WR_DMA_DDAR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_DMA_DDAR,32,DATA)/************************************************************************ USART Module Registers Description************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_UART0_UMR (0x0100) /* RW */#define MCF5272_UART0_USR (0x0104) /* USR RO, UCSR WO */#define MCF5272_UART0_UCR (0x0108) /* WO */#define MCF5272_UART0_UBUF (0x010C) /* URB RO, UTB WO */#define MCF5272_UART0_UCCR (0x0110) /* UCCR RO, UACR WO */#define MCF5272_UART0_UISR (0x0114) /* UISR RO, UIMR WO */#define MCF5272_UART0_UBG1 (0x0118) /* WO */#define MCF5272_UART0_UBG2 (0x011C) /* WO */#define MCF5272_UART0_UABR1 (0x0120) /* RO */#define MCF5272_UART0_UABR2 (0x0124) /* RO */#define MCF5272_UART0_UTFCSR (0x0128) /* RW */#define MCF5272_UART0_URFCSR (0x012C) /* RW */#define MCF5272_UART0_UIP (0x0134) /* RO */#define MCF5272_UART0_UOP1 (0x0138) /* WO */#define MCF5272_UART0_UOP0 (0x013C) /* WO */#define MCF5272_UART1_UMR (0x0140) /* RW */#define MCF5272_UART1_USR (0x0144) /* USR RO, UCSR WO */#define MCF5272_UART1_UCR (0x0148) /* WO */#define MCF5272_UART1_UBUF (0x014C) /* URB RO, UTB WO */#define MCF5272_UART1_UCCR (0x0150) /* UCCR RO, UACR WO */#define MCF5272_UART1_UISR (0x0154) /* UISR RO, UIMR WO */#define MCF5272_UART1_UBG1 (0x0158) /* WO */#define MCF5272_UART1_UBG2 (0x015C) /* WO */#define MCF5272_UART1_UABR1 (0x0160) /* RO */#define MCF5272_UART1_UABR2 (0x0164) /* RO */#define MCF5272_UART1_UTFCSR (0x0168) /* RW */#define MCF5272_UART1_URFCSR (0x016C) /* RW */#define MCF5272_UART1_UIP (0x0174) /* RO */#define MCF5272_UART1_UOP1 (0x0178) /* WO */#define MCF5272_UART1_UOP0 (0x017C) /* WO *//* Read access macros for general use */#define MCF5272_RD_UART0_UMR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_UMR,8)#define MCF5272_RD_UART0_USR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_USR,8)#define MCF5272_RD_UART0_URB(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_UBUF,8)#define MCF5272_RD_UART0_UCCR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_UCCR,8)#define MCF5272_RD_UART0_UISR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_UISR,8)#define MCF5272_RD_UART0_UABR1(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_UABR1,8)#define MCF5272_RD_UART0_UABR2(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UABR2,8)#define MCF5272_RD_UART0_UTFCSR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_UTFCSR,8)#define MCF5272_RD_UART0_URFCSR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_URFCSR,8)#define MCF5272_RD_UART0_UIP(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART0_UIP,8)#define MCF5272_RD_UART1_UMR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UMR,8)#define MCF5272_RD_UART1_USR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_USR,8)#define MCF5272_RD_UART1_URB(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UBUF,8)#define MCF5272_RD_UART1_UCCR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UCCR,8)#define MCF5272_RD_UART1_UISR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UISR,8)#define MCF5272_RD_UART1_UABR1(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UABR1,8)#define MCF5272_RD_UART1_UABR2(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UABR2,8)#define MCF5272_RD_UART1_UTFCSR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UTFCSR,8)#define MCF5272_RD_UART1_URFCSR(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_URFCSR,8)#define MCF5272_RD_UART1_UIP(IMMP) \ Mcf5272_iord(IMMP,MCF5272_UART1_UIP,8)/* Write access macros for general use */#define MCF5272_WR_UART0_UMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UMR,8,DATA)#define MCF5272_WR_UART0_UCSR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_USR,8,DATA)#define MCF5272_WR_UART0_UCR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UCR,8,DATA)#define MCF5272_WR_UART0_UTB(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UBUF,8,DATA)#define MCF5272_WR_UART0_UACR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UCCR,8,DATA)#define MCF5272_WR_UART0_UIMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UISR,8,DATA)#define MCF5272_WR_UART0_UBG1(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UBG1,8,DATA)#define MCF5272_WR_UART0_UBG2(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UBG2,8,DATA)#define MCF5272_WR_UART0_UTFCSR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UTFCSR,8,DATA)#define MCF5272_WR_UART0_URFCSR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_URFCSR,8,DATA)#define MCF5272_WR_UART0_UOP1(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UOP1,8,DATA)#define MCF5272_WR_UART0_UOP0(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART0_UOP0,8,DATA)#define MCF5272_WR_UART1_UMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UMR,8,DATA)#define MCF5272_WR_UART1_UCSR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_USR,8,DATA)#define MCF5272_WR_UART1_UCR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UCR,8,DATA)#define MCF5272_WR_UART1_UTB(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UBUF,8,DATA)#define MCF5272_WR_UART1_UACR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UCCR,8,DATA)#define MCF5272_WR_UART1_UIMR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UISR,8,DATA)#define MCF5272_WR_UART1_UBG1(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UBG1,8,DATA)#define MCF5272_WR_UART1_UBG2(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UBG2,8,DATA)#define MCF5272_WR_UART1_UTFCSR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UTFCSR,8,DATA)#define MCF5272_WR_UART1_URFCSR(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_URFCSR,8,DATA)#define MCF5272_WR_UART1_UOP1(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UOP1,8,DATA)#define MCF5272_WR_UART1_UOP0(IMMP,DATA) \ Mcf5272_iowr(IMMP,MCF5272_UART1_UOP0,8,DATA)/* Bit level definitions and macros */#define MCF5272_UART_UMR1_RXRTS (0x80)#define MCF5272_UART_UMR1_RXIRQ (0x40)#define MCF5272_UART_UMR1_ERR (0x20)#define MCF5272_UART_UMR1_PM_MULTI_ADDR (0x1C)#define MCF5272_UART_UMR1_PM_MULTI_DATA (0x18)#define MCF5272_UART_UMR1_PM_NONE (0x10)#define MCF5272_UART_UMR1_PM_FORCE_HI (0x0C)#define MCF5272_UART_UMR1_PM_FORCE_LO (0x08)#define MCF5272_UART_UMR1_PM_ODD (0x04)#define MCF5272_UART_UMR1_PM_EVEN (0x00)#define MCF5272_UART_UMR1_BC_5 (0x00)#define MCF5272_UART_UMR1_BC_6 (0x01)#define MCF5272_UART_UMR1_BC_7 (0x02)⌨️ 快捷键说明
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