📄 mcf5272.h

📁 完整的Bell实验室的嵌入式文件系统TFS
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#define MCF5272_SIM_PMR_DMAPDN      0x00800000#define MCF5272_SIM_PMR_PWMPDN      0x00400000#define MCF5272_SIM_PMR_QSPIPDN     0x00200000#define MCF5272_SIM_PMR_TIMERPDN    0x00100000#define MCF5272_SIM_PMR_GPIOPDN     0x00080000#define MCF5272_SIM_PMR_USBPDN      0x00040000#define MCF5272_SIM_PMR_UART1PDN    0x00020000#define MCF5272_SIM_PMR_UART0PDN    0x00010000#define MCF5272_SIM_PMR_USBWK       0x00000400#define MCF5272_SIM_PMR_UART1WK     0x00000200#define MCF5272_SIM_PMR_UART0WK     0x00000100#define MCF5272_SIM_PMR_MOS         0x00000020#define MCF5272_SIM_PMR_SLPEN       0x00000010/************************************************************************ Interrupt Controller Registers************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_SIM_ICR1        (0x0020)#define MCF5272_SIM_ICR2        (0x0024)#define MCF5272_SIM_ICR3        (0x0028)#define MCF5272_SIM_ICR4        (0x002C)#define MCF5272_SIM_ISR         (0x0030)#define MCF5272_SIM_PITR        (0x0034)#define MCF5272_SIM_PIWR        (0x0038)#define MCF5272_SIM_PIVR        (0x003F)/* Read access macros for general use */#define MCF5272_RD_SIM_ICR1(IMMP)   Mcf5272_iord(IMMP,MCF5272_SIM_ICR1,32)#define MCF5272_RD_SIM_ICR2(IMMP)   Mcf5272_iord(IMMP,MCF5272_SIM_ICR2,32)#define MCF5272_RD_SIM_ICR3(IMMP)   Mcf5272_iord(IMMP,MCF5272_SIM_ICR3,32)#define MCF5272_RD_SIM_ICR4(IMMP)   Mcf5272_iord(IMMP,MCF5272_SIM_ICR4,32)#define MCF5272_RD_SIM_ISR(IMMP)    Mcf5272_iord(IMMP,MCF5272_SIM_ISR,32)#define MCF5272_RD_SIM_PITR(IMMP)   Mcf5272_iord(IMMP,MCF5272_SIM_PITR,32)#define MCF5272_RD_SIM_PIWR(IMMP)   Mcf5272_iord(IMMP,MCF5272_SIM_PIWR,32)#define MCF5272_RD_SIM_PIVR(IMMP)   Mcf5272_iord(IMMP,MCF5272_SIM_PIVR,8)/* Write access macros for general use */#define MCF5272_WR_SIM_ICR1(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_SIM_ICR1,32,DATA)#define MCF5272_WR_SIM_ICR2(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_SIM_ICR2,32,DATA)#define MCF5272_WR_SIM_ICR3(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_SIM_ICR3,32,DATA)#define MCF5272_WR_SIM_ICR4(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_SIM_ICR4,32,DATA)#define MCF5272_WR_SIM_PITR(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_SIM_PITR,32,DATA)#define MCF5272_WR_SIM_PIWR(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_SIM_PIWR,32,DATA)#define MCF5272_WR_SIM_PIVR(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_SIM_PIVR,8,DATA)/* Bit level definitions and macros */#define MCF5272_SIM_ICR_INT1_IL(a)  ( 0x80000000 | (((a)&0x07)<<28) )#define MCF5272_SIM_ICR_INT2_IL(a)  ( 0x08000000 | (((a)&0x07)<<24) )#define MCF5272_SIM_ICR_INT3_IL(a)  ( 0x00800000 | (((a)&0x07)<<20) )#define MCF5272_SIM_ICR_INT4_IL(a)  ( 0x00080000 | (((a)&0x07)<<16) )#define MCF5272_SIM_ICR_TMR0_IL(a)  ( 0x00008000 | (((a)&0x07)<<12) )#define MCF5272_SIM_ICR_TMR1_IL(a)  ( 0x00000800 | (((a)&0x07)<<8) )#define MCF5272_SIM_ICR_TMR2_IL(a)  ( 0x00000080 | (((a)&0x07)<<4) )#define MCF5272_SIM_ICR_TMR3_IL(a)  ( 0x00000008 | ((a)&0x07) )#define MCF5272_SIM_ICR_TMR_IL(a,x) ( (0x8 | ((a)&0x07)) << ((3-x)*4))#define MCF5272_SIM_ICR_UART0_IL(a) ( 0x80000000 | (((a)&0x07)<<28) )#define MCF5272_SIM_ICR_UART1_IL(a) ( 0x08000000 | (((a)&0x07)<<24) )#define MCF5272_SIM_ICR_PLIP_IL(a)  ( 0x00800000 | (((a)&0x07)<<20) )#define MCF5272_SIM_ICR_PLIA_IL(a)  ( 0x00080000 | (((a)&0x07)<<16) )#define MCF5272_SIM_ICR_USB0_IL(a)  ( 0x00008000 | (((a)&0x07)<<12) )#define MCF5272_SIM_ICR_USB1_IL(a)  ( 0x00000800 | (((a)&0x07)<<8) )#define MCF5272_SIM_ICR_USB2_IL(a)  ( 0x00000800 | (((a)&0x07)<<4) )#define MCF5272_SIM_ICR_USB3_IL(a)  ( 0x00000800 | ((a)&0x07) )#define MCF5272_SIM_ICR_USB4_IL(a)  ( 0x80000000 | (((a)&0x07)<<28) )#define MCF5272_SIM_ICR_USB5_IL(a)  ( 0x08000000 | (((a)&0x07)<<24) )#define MCF5272_SIM_ICR_USB6_IL(a)  ( 0x00800000 | (((a)&0x07)<<20) )#define MCF5272_SIM_ICR_USB7_IL(a)  ( 0x00080000 | (((a)&0x07)<<16) )#define MCF5272_SIM_ICR_DMA_IL(a)   ( 0x00008000 | (((a)&0x07)<<12) )#define MCF5272_SIM_ICR_ERX_IL(a)   ( 0x00000800 | (((a)&0x07)<<8) )#define MCF5272_SIM_ICR_ETX_IL(a)   ( 0x00000080 | (((a)&0x07)<<4) )#define MCF5272_SIM_ICR_ENTC_IL(a)  ( 0x00000008 | ((a)&0x07) )#define MCF5272_SIM_ICR_QSPI_IL(a)  ( 0x80000000 | (((a)&0x07)<<28) )#define MCF5272_SIM_ICR_INT5_IL(a)  ( 0x08000000 | (((a)&0x07)<<24) )#define MCF5272_SIM_ICR_INT6_IL(a)  ( 0x00800000 | (((a)&0x07)<<20) )#define MCF5272_SIM_ICR_SWTO_IL(a)  ( 0x00080000 | (((a)&0x07)<<16) )#define MCF5272_SIM_PITR_POS_EDGE   (0xF0000060)#define MCF5272_SIM_PITR_NEG_EDGE   (0x00000000)#define MCF5272_SIM_PIWR_INT1           (0x80000000)#define MCF5272_SIM_PIWR_INT2           (0x40000000)#define MCF5272_SIM_PIWR_INT3           (0x20000000)#define MCF5272_SIM_PIWR_INT4           (0x10000000)#define MCF5272_SIM_PIWR_TMR0           (0x08000000)#define MCF5272_SIM_PIWR_TMR1           (0x04000000)#define MCF5272_SIM_PIWR_TMR2           (0x02000000)#define MCF5272_SIM_PIWR_TMR3           (0x01000000)#define MCF5272_SIM_PIWR_UART0      (0x00800000)#define MCF5272_SIM_PIWR_UART1      (0x00400000)#define MCF5272_SIM_PIWR_PLIP           (0x00200000)#define MCF5272_SIM_PIWR_PLIA           (0x00100000)#define MCF5272_SIM_PIWR_USB_0          (0x00080000)#define MCF5272_SIM_PIWR_USB_1          (0x00040000)#define MCF5272_SIM_PIWR_USB_2          (0x00020000)#define MCF5272_SIM_PIWR_USB_3          (0x00010000)#define MCF5272_SIM_PIWR_USB_4          (0x00008000)#define MCF5272_SIM_PIWR_USB_5          (0x00004000)#define MCF5272_SIM_PIWR_USB_6          (0x00002000)#define MCF5272_SIM_PIWR_USB_7          (0x00001000)#define MCF5272_SIM_PIWR_DMA            (0x00000800)#define MCF5272_SIM_PIWR_ERx            (0x00000400)#define MCF5272_SIM_PIWR_ETx            (0x00000200)#define MCF5272_SIM_PIWR_ENTC           (0x00000100)#define MCF5272_SIM_PIWR_QSPI           (0x00000080)#define MCF5272_SIM_PIWR_INT5           (0x00000040)#define MCF5272_SIM_PIWR_INT6           (0x00000020)#define MCF5272_SIM_PIWR_SWTO           (0x00000010)#define MCF5272_SIM_PIVR_IL(a)      (((a)&0x07)<<5)#define MCF5272_SIM_PIVR_NORMAL     (0x40)/************************************************************************ Chip Select Registers************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_CS_CSBR0    (0x0040)#define MCF5272_CS_CSOR0    (0x0044)#define MCF5272_CS_CSBR1    (0x0048)#define MCF5272_CS_CSOR1    (0x004C)#define MCF5272_CS_CSBR2    (0x0050)#define MCF5272_CS_CSOR2    (0x0054)#define MCF5272_CS_CSBR3    (0x0058)#define MCF5272_CS_CSOR3    (0x005C)#define MCF5272_CS_CSBR4    (0x0060)#define MCF5272_CS_CSOR4    (0x0064)#define MCF5272_CS_CSBR5    (0x0068)#define MCF5272_CS_CSOR5    (0x006C)#define MCF5272_CS_CSBR6    (0x0070)#define MCF5272_CS_CSOR6    (0x0074)#define MCF5272_CS_CSBR7    (0x0078)#define MCF5272_CS_CSOR7    (0x007C)/* Read access macros for general use */#define MCF5272_RD_CS_CSBR0(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSBR0,32)#define MCF5272_RD_CS_CSOR0(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSOR0,32)#define MCF5272_RD_CS_CSBR1(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSBR1,32)#define MCF5272_RD_CS_CSOR1(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSOR1,32)#define MCF5272_RD_CS_CSBR2(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSBR2,32)#define MCF5272_RD_CS_CSOR2(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSOR2,32)#define MCF5272_RD_CS_CSBR3(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSBR3,32)#define MCF5272_RD_CS_CSOR3(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSOR3,32)#define MCF5272_RD_CS_CSBR4(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSBR4,32)#define MCF5272_RD_CS_CSOR4(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSOR4,32)#define MCF5272_RD_CS_CSBR5(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSBR5,32)#define MCF5272_RD_CS_CSOR5(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSOR5,32)#define MCF5272_RD_CS_CSBR6(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSBR6,32)#define MCF5272_RD_CS_CSOR6(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSOR6,32)#define MCF5272_RD_CS_CSBR7(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSBR7,32)#define MCF5272_RD_CS_CSOR7(IMMP)   Mcf5272_iord(IMMP,MCF5272_CS_CSOR7,32)/* Write access macros for general use */#define MCF5272_WR_CS_CSBR0(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSBR0,32,DATA)#define MCF5272_WR_CS_CSOR0(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSOR0,32,DATA)#define MCF5272_WR_CS_CSBR1(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSBR1,32,DATA)#define MCF5272_WR_CS_CSOR1(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSOR1,32,DATA)#define MCF5272_WR_CS_CSBR2(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSBR2,32,DATA)#define MCF5272_WR_CS_CSOR2(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSOR2,32,DATA)#define MCF5272_WR_CS_CSBR3(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSBR3,32,DATA)#define MCF5272_WR_CS_CSOR3(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSOR3,32,DATA)#define MCF5272_WR_CS_CSBR4(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSBR4,32,DATA)#define MCF5272_WR_CS_CSOR4(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSOR4,32,DATA)#define MCF5272_WR_CS_CSBR5(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSBR5,32,DATA)#define MCF5272_WR_CS_CSOR5(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSOR5,32,DATA)#define MCF5272_WR_CS_CSBR6(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSBR6,32,DATA)#define MCF5272_WR_CS_CSOR6(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSOR6,32,DATA)#define MCF5272_WR_CS_CSBR7(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSBR7,32,DATA)#define MCF5272_WR_CS_CSOR7(IMMP,DATA)  \    Mcf5272_iowr(IMMP,MCF5272_CS_CSOR7,32,DATA)/* Bit level definitions and macros */#define MCF5272_CS_BR_BASE(a)           ((a)&0xFFFFF000)#define MCF5272_CS_OR_MASK_32M          (0xFE000000)#define MCF5272_CS_OR_MASK_16M          (0xFF000000)#define MCF5272_CS_OR_MASK_8M           (0xFF800000)#define MCF5272_CS_OR_MASK_4M           (0xFFC00000)#define MCF5272_CS_OR_MASK_2M           (0xFFE00000)#define MCF5272_CS_OR_MASK_1M           (0xFFF00000)#define MCF5272_CS_OR_MASK_512K         (0xFFF80000)#define MCF5272_CS_OR_MASK_256K         (0xFFFC0000)#define MCF5272_CS_OR_MASK_128K         (0xFFFE0000)#define MCF5272_CS_OR_MASK_64K          (0xFFFF0000)#define MCF5272_CS_OR_MASK_32K          (0xFFFF8000)#define MCF5272_CS_OR_MASK_16K          (0xFFFFC000)#define MCF5272_CS_OR_MASK_8K           (0xFFFFE000)#define MCF5272_CS_OR_MASK_4K           (0xFFFFF000)#define MCF5272_CS_OR_WS_MASK           (0x007C)#define MCF5272_CS_OR_WS(a)             (((a)&0x1F)<<2)#define MCF5272_CS_OR_BRST              (0x0100)#define MCF5272_CS_OR_RD                (0x0003)#define MCF5272_CS_OR_WR                (0x0001)#define MCF5272_CS_BR_PS_8              (0x0100)#define MCF5272_CS_BR_PS_16             (0x0200)#define MCF5272_CS_BR_PS_32             (0x0000)#define MCF5272_CS_BR_PS_LINE           (0x0300)#define MCF5272_CS_BR_ROM               (0x0000)#define MCF5272_CS_BR_SRAM              (0x0000)#define MCF5272_CS_BR_SRAM_8            (0x0C00)#define MCF5272_CS_BR_SDRAM             (0x0400)#define MCF5272_CS_BR_ISA               (0x0800)#define MCF5272_CS_BR_SV                (0x0080)#define MCF5272_CS_BR_EN                (0x0001)/************************************************************************ Ports Registers Description************************************************************************//* Offsets of the registers from the MBAR */#define MCF5272_GPIO_PACNT      (0x0080)#define MCF5272_GPIO_PADDR      (0x0084)#define MCF5272_GPIO_PADAT      (0x0086)#define MCF5272_GPIO_PBCNT      (0x0088)#define MCF5272_GPIO_PBDDR      (0x008C)#define MCF5272_GPIO_PBDAT      (0x008E)#define MCF5272_GPIO_PCDDR      (0x0094)#define MCF5272_GPIO_PCDAT      (0x0096)#define MCF5272_GPIO_PDCNT      (0x0098)/* Read access macros for general use */#define MCF5272_RD_GPIO_PACNT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PACNT,32)#define MCF5272_RD_GPIO_PADDR(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PADDR,16)#define MCF5272_RD_GPIO_PADAT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PADAT,16)#define MCF5272_RD_GPIO_PBCNT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PBCNT,32)#define MCF5272_RD_GPIO_PBDDR(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PBDDR,16)#define MCF5272_RD_GPIO_PBDAT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PBDAT,16)#define MCF5272_RD_GPIO_PCDDR(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PCDDR,16)#define MCF5272_RD_GPIO_PCDAT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PCDAT,16)#define MCF5272_RD_GPIO_PDCNT(IMMP) Mcf5272_iord(IMMP,MCF5272_GPIO_PDCNT,32)/* Write access macros for general use */#define MCF5272_WR_GPIO_PACNT(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PACNT,32,DATA)#define MCF5272_WR_GPIO_PADDR(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PADDR,16,DATA)#define MCF5272_WR_GPIO_PADAT(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PADAT,16,DATA)#define MCF5272_WR_GPIO_PBCNT(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PBCNT,32,DATA)#define MCF5272_WR_GPIO_PBDDR(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PBDDR,16,DATA)#define MCF5272_WR_GPIO_PBDAT(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PBDAT,16,DATA)#define MCF5272_WR_GPIO_PCDDR(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PCDDR,16,DATA)#define MCF5272_WR_GPIO_PCDAT(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PCDAT,16,DATA)#define MCF5272_WR_GPIO_PDCNT(IMMP,DATA)    \    Mcf5272_iowr(IMMP,MCF5272_GPIO_PDCNT,32,DATA)/* Bit level definitions and macros */#define MCF5272_GPIO_DDR15_INPUT    (~0x80)#define MCF5272_GPIO_DDR15_OUTPUT   ( 0x80)#define MCF5272_GPIO_DDR14_INPUT    (~0x40)#define MCF5272_GPIO_DDR14_OUTPUT   ( 0x40)#define MCF5272_GPIO_DDR13_INPUT    (~0x20)#define MCF5272_GPIO_DDR13_OUTPUT   ( 0x20)#define MCF5272_GPIO_DDR12_INPUT    (~0x10)#define MCF5272_GPIO_DDR12_OUTPUT   ( 0x10)#define MCF5272_GPIO_DDR11_INPUT    (~0x08)#define MCF5272_GPIO_DDR11_OUTPUT   ( 0x08)#define MCF5272_GPIO_DDR10_INPUT    (~0x04)#define MCF5272_GPIO_DDR10_OUTPUT   ( 0x04)
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