reset.s

完整的Bell实验室的嵌入式文件系统TFS

/* reset.s:
 * First bit of boot code run by the processor.
 *
 * General notice:
 * This code is part of a boot-monitor package developed as a generic base
 * platform for embedded system designs.  As such, it is likely to be
 * distributed to various projects beyond the control of the original
 * author.  Please notify the author of any enhancements made or bugs found
 * so that all may benefit from the changes.  In addition, notification back
 * to the author will allow the new user to pick up changes that may have
 * been made by other users after this version of the code was distributed.
 *
 * Author:  Ed Sutter
 * email:   [e-mail]      (home: [e-mail])
 * phone:   [phone]            (home: 908-889-5161)
 *
 * Notes:
 * The following registers are understood by GAS for ColdFire...
 *  cacr(0x002), tc(0x003), acr0(0x004), acr1(0x005), acr2(0x006),
 *  acr3(0x007), vbr(0x801), rombar(0xC00), rambar0(0xC04),
 *  rambar1(0xC05), mbar(0xC0F)
 *
 * This code was derived from source code from Motorola...
 *
 *********************************************************************
 *
 * Copyright:
 *  MOTOROLA, INC. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of Motorola, Inc. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, MOTOROLA 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  Motorola assumes no responsibility for the maintenance and support
 *  of this software
 ********************************************************************
 */

#include "cpuio.h"
#include "warmstart.h"
    
    .file   "reset.s"

    .equ IMMaddr,0x10000000
    .equ SRAMaddr,0xe0000000    /* Base address of .5K of internal SRAM */
    .equ SRAMsize,4096          /* 4K Byte SRAM, organized as 1K * 32 bits */
    .equ STACKsize,2048
    .equ STACKtop,STACKsize-4

    .align  2
    .bss
    .comm   MonStack, STACKsize

    .global etheraddr
    .global ipaddr
    .global coldstart
    .global warmstart
    .global moncomptr
    .global VECTOR_TABLE
    .global resetSP
    .global resetPC
    .extern moncom

    .text

VECTOR_TABLE:
resetSP:
    .long   SRAMaddr+SRAMsize   /* Initial SP = end of internal SRAM */
resetPC:
    .long   0x400               /* Initial PC */

/* Put the rest of the vector table here.
 */

/* 
 * At power-on reset, the initial PC must be between 0-4K so that 
 * CS0 will assert for accesses to Flash.  At this point, we need to
 * clear the CS0 address mask and change the PC to the real Flash 
 * location of 0xFFE00000.  This must be done before any branch or
 * jump instruction is executed!
 */
    .org    0x400
coldstart:
    move.l      #IMMaddr+1,%d0
    movec       %d0,%MBAR
    move.l      #IMMaddr,%a0
    move.l      #0x20,%d0
    move.l      %d0,0x44(%a0)
    nop
    jmp         new_addr        

new_addr:
    nop
    move.l      #INITIALIZE,%d5
    jmp         continue;

etheraddr:
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
ipaddr:
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
    .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff

moncomptr:                      /* Pointer to the moncom function, used */
    .long   moncom              /* to link application to monitor. */

/* The tag "warmstart" is called by 'C', so put the argument into reg D5.
 * The content of D5 must be preserved until start() is called so
 * that it can be used as the argument passed into start().
 */
warmstart:
    move.l      %sp@(4),%d5

continue:
    move.w      #0x2700,%SR
    move.l      #VECTOR_TABLE,%d0
    movec       %d0,%VBR

    /* Invalidate the cache and disable it */
    move.l  #0x01000000,%d0
    movec   %d0,%cacr

    /* Disable ACRs */
    moveq.l #0,%d0
    movec   %d0,%ACR0
    movec   %d0,%ACR1

    /* Initialize SRAMBAR: locate SRAM and validate it */
    move.l  #0xE0000021,%d0
    movec   %d0,%RAMBAR0

    /* Point SP into SRAM (temporarily).  SRAM is used as stack space
     * while initializing the MCF5206 periphs and memory controller.
     */
    move.l      #SRAMaddr+SRAMsize,%sp

    /* Obtain pointer to where MBAR is to be mapped */
    jsr     mcf5272_mbar
    move.l  %d0,%d6

    /* Obtain pointer to where RAMBAR is to be mapped */
    jsr     mcf5272_rambar

    /* Adjust SP to (soon to be valid) SRAM */
    move.l  %d0,%a0
    lea     SRAMsize(%a0),%sp

    /* Map RAMBAR and MBAR */
    ori.l   #0x21,%d0           /* Set Valid and C/I bit */
    movec   %d0,%RAMBAR0

    move.l  %d6,%d0
    addq.l  #1,%d0              /* Set Valid bit */
    movec   %d0,%MBAR

    /* Initialize mcf5272 periphs, etc */
    move.l  %d6,-(%sp)          /* pointer to internal resources */
    jsr     mcf5272_init


    /* Point SP to DRAM.  DRAM may only be visible once CS0
     * de-activated as global chipselect.
     */
    move.l      #MonStack+STACKtop,%sp

    move.l      %d5,%sp@-
    jsr         start

    /* Should never get here: */
badnews:
    halt


/********************************************************************
 * Miscellaneous assembler functions:
 */
    .global putsr
    .global getsr
    .global getsp
    .global getcacr

putsr:
    move.l      %sp@(4),%d0
    move.w      %d0,%sr
    rts
    
getsr:
    move.l      #0,%d0
    move.w      %sr,%d0
    rts

getsp:
    move.l      %sp,%d0
    rts


/********************************************************************
 * mcf5272 has Icache only
 */
cpu_cache_flush:
    nop                     /* sync */
    move.l  #0x01000000,%d0 /* Invalidate the I-Cache */
    movec %d0,%cacr
    rts

/********************************************************************
 * These routines write to the special purpose registers in the ColdFire
 * core.  Since these registers are write-only in the supervisor model,
 * no corresponding read routines exist.
 */
    .global mcf5272_wr_vbr
mcf5272_wr_vbr:
    move.l  %sp@(4),%d0
    andi.l  #0xFFF00000,%d0 /* align to 1M boundary  */
    movec   %d0,%VBR
    nop
    rts

    .global mcf5272_wr_cacr
mcf5272_wr_cacr:
    move.l  %sp@(4),%d0
    movec %d0,%cacr
    nop
    rts

    .global mcf5272_wr_acr0
mcf5272_wr_acr0:
    move.l  %sp@(4),%d0
    movec %d0,%ACR0
    nop
    rts

    .global mcf5272_wr_acr1
mcf5272_wr_acr1:
    move.l  %sp@(4),%d0
    movec %d0,%ACR1
    nop
    rts

    .global mcf5272_wr_rambar
mcf5272_wr_rambar:
    move.l  %sp@(4),%d0
    movec %d0,%RAMBAR0
    nop
    rts

    .global mcf5272_wr_mbar
mcf5272_wr_mbar:
    move.l  %sp@(4),%d0
    movec %d0,%MBAR
    nop
    rts
    
    .global mcf5272_wr_sr
mcf5272_wr_sr:
    move.l  %sp@(4),%d0
    move.l  4(%sp),%d0
    move.w  %d0,%SR
    rts