📄 ocpuio.h
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#define MCF5206_CS_DMCR_AA (0x0100)#define MCF5206_CS_DMCR_PS_8 (0x0040)#define MCF5206_CS_DMCR_PS_16 (0x0080)#define MCF5206_CS_DMCR_PS_32 (0x0000)#define MCF5206_CS_DMCR_EMAA (0x0020)#define MCF5206_CS_DMCR_WRAH (0x0008)#define MCF5206_CS_DMCR_RDAH (0x0004)#define MCF5206_IACK_ADDRESS (MCF5206_CS_CSAR_BASE(0xFFFFFFE0))#define MCF5206_IACK_MASK (MCF5206_CS_CSMR_MASK_64K)typedef volatile struct{ NATURAL16 reserved1[0x23]; NATURAL16 DCRR; NATURAL16 reserved2; NATURAL16 DCTR; NATURAL16 DCAR0; NATURAL16 reserved4; NATURAL32 DCMR0; NATURAL8 reserved5[3]; NATURAL8 DCCR0; NATURAL16 DCAR1; NATURAL16 reserved6; NATURAL32 DCMR1; NATURAL8 reserved7[3]; NATURAL8 DCCR1;} MCF5206_DRAMC;#define MCF5206_DRAMC_DCRR_RC(a) ((a)&0x0FFF)#define MCF5206_DRAMC_DCTR_DAEM (0x8000)#define MCF5206_DRAMC_DCTR_EDO (0x4000)#define MCF5206_DRAMC_DCTR_RCD (0x1000)#define MCF5206_DRAMC_DCTR_RSH_1 (0x0000)#define MCF5206_DRAMC_DCTR_RSH_2 (0x0200)#define MCF5206_DRAMC_DCTR_RSH_3 (0x0400)#define MCF5206_DRAMC_DCTR_CRP_15 (0x0000)#define MCF5206_DRAMC_DCTR_CRP_25 (0x0020)#define MCF5206_DRAMC_DCTR_CRP_35 (0x0040)#define MCF5206_DRAMC_DCTR_CAS (0x0008)#define MCF5206_DRAMC_DCTR_CP (0x0002)#define MCF5206_DRAMC_DCTR_CSR (0x0001)#define MCF5206_DRAMC_DCAR_BASE(a) (((a)&0xFFFE0000)>>16)#define MCF5206_DRAMC_DCMR_MASK_128M (0x07FE0000)#define MCF5206_DRAMC_DCMR_MASK_64M (0x03FE0000)#define MCF5206_DRAMC_DCMR_MASK_32M (0x01FE0000)#define MCF5206_DRAMC_DCMR_MASK_16M (0x00FE0000)#define MCF5206_DRAMC_DCMR_MASK_8M (0x007E0000)#define MCF5206_DRAMC_DCMR_MASK_4M (0x003E0000)#define MCF5206_DRAMC_DCMR_MASK_2M (0x001E0000)#define MCF5206_DRAMC_DCMR_MASK_1M (0x000E0000)#define MCF5206_DRAMC_DCMR_MASK_1024K (0x00060000)#define MCF5206_DRAMC_DCMR_MASK_256K (0x00020000)#define MCF5206_DRAMC_DCMR_MASK_128K (0x00000000)#define MCF5206_DRAMC_DCMR_SC (0x00000010)#define MCF5206_DRAMC_DCMR_SD (0x00000008)#define MCF5206_DRAMC_DCMR_UC (0x00000004)#define MCF5206_DRAMC_DCMR_UD (0x00000002)#define MCF5206_DRAMC_DCCR_PS_32 (0x00)#define MCF5206_DRAMC_DCCR_PS_16 (0xC0)#define MCF5206_DRAMC_DCCR_PS_8 (0x40)#define MCF5206_DRAMC_DCCR_PS_MASK (0xC0)#define MCF5206_DRAMC_DCCR_BPS_512B (0x00)#define MCF5206_DRAMC_DCCR_BPS_1K (0x10)#define MCF5206_DRAMC_DCCR_BPS_2K (0x20)#define MCF5206_DRAMC_DCCR_PM_NORMAL (0x00)#define MCF5206_DRAMC_DCCR_PM_BURSTPAGE (0x04)#define MCF5206_DRAMC_DCCR_PM_FASTPAGE (0x0C)#define MCF5206_DRAMC_DCCR_WR (0x02)#define MCF5206_DRAMC_DCCR_RD (0x01)typedef volatile struct{ NATURAL8 reserved0[0x100]; NATURAL16 TMR1; NATURAL16 reserved1; NATURAL16 TRR1; NATURAL16 reserved2; NATURAL16 TCR1; NATURAL16 reserved3; NATURAL16 TCN1; NATURAL16 reserved4; NATURAL8 reserved5; NATURAL8 TER1; NATURAL32 reserved6; NATURAL32 reserved7; NATURAL32 reserved8; NATURAL16 TMR2; NATURAL16 reserved9; NATURAL16 TRR2; NATURAL16 reserved10; NATURAL16 TCR2; NATURAL16 reserved11; NATURAL16 TCN2; NATURAL16 reserved12; NATURAL8 reserved13; NATURAL8 TER2;} MCF5206_TIMER;#define MCF5206_TIMER_TMR_PS(a) (((a)&0x00FF)<<8)#define MCF5206_TIMER_TMR_CE_ANY (0x00C0)#define MCF5206_TIMER_TMR_CE_RISE (0x0080)#define MCF5206_TIMER_TMR_CE_FALL (0x0040)#define MCF5206_TIMER_TMR_CE_NONE (0x0000)#define MCF5206_TIMER_TMR_OM (0x0020)#define MCF5206_TIMER_TMR_ORI (0x0010)#define MCF5206_TIMER_TMR_FRR (0x0008)#define MCF5206_TIMER_TMR_CLK_TIN (0x0006)#define MCF5206_TIMER_TMR_CLK_DIV16 (0x0004)#define MCF5206_TIMER_TMR_CLK_MSCLK (0x0002)#define MCF5206_TIMER_TMR_CLK_STOP (0x0000)#define MCF5206_TIMER_TMR_RST (0x0001)#define MCF5206_TIMER_TER_REF (0x02)#define MCF5206_TIMER_TER_CAP (0x01)typedef volatile struct{ NATURAL32 reserved1[0x140>>2]; NATURAL8 UMR; NATURAL8 reserved2; NATURAL8 reserved3; NATURAL8 reserved4; NATURAL8 USR; NATURAL8 reserved5; NATURAL8 reserved6; NATURAL8 reserved7; NATURAL8 UCR; NATURAL8 reserved8; NATURAL8 reserved9; NATURAL8 reserved10; NATURAL8 UBUF; NATURAL8 reserved11; NATURAL8 reserved12; NATURAL8 reserved13; NATURAL8 UACR; NATURAL8 reserved14; NATURAL8 reserved15; NATURAL8 reserved16; NATURAL8 UIR; NATURAL8 reserved17; NATURAL8 reserved18; NATURAL8 reserved19; NATURAL8 UBG1; NATURAL8 reserved20; NATURAL8 reserved21; NATURAL8 reserved22; NATURAL8 UBG2; NATURAL32 reserved23[4]; NATURAL8 UIVR; NATURAL8 reserved24; NATURAL8 reserved25; NATURAL8 reserved26; NATURAL8 UIP; NATURAL8 reserved27; NATURAL8 reserved28; NATURAL8 reserved29; NATURAL8 UOP1; NATURAL8 reserved30; NATURAL8 reserved31; NATURAL8 reserved32; NATURAL8 UOP0;} MCF5206_UART1;typedef volatile struct{ NATURAL32 reserved1[0x180>>2]; NATURAL8 UMR; NATURAL8 reserved2; NATURAL8 reserved3; NATURAL8 reserved4; NATURAL8 USR; NATURAL8 reserved5; NATURAL8 reserved6; NATURAL8 reserved7; NATURAL8 UCR; NATURAL8 reserved8; NATURAL8 reserved9; NATURAL8 reserved10; NATURAL8 UBUF; NATURAL8 reserved11; NATURAL8 reserved12; NATURAL8 reserved13; NATURAL8 UACR; NATURAL8 reserved14; NATURAL8 reserved15; NATURAL8 reserved16; NATURAL8 UIR; NATURAL8 reserved17; NATURAL8 reserved18; NATURAL8 reserved19; NATURAL8 UBG1; NATURAL8 reserved20; NATURAL8 reserved21; NATURAL8 reserved22; NATURAL8 UBG2; NATURAL32 reserved23[4]; NATURAL8 UIVR; NATURAL8 reserved24; NATURAL8 reserved25; NATURAL8 reserved26; NATURAL8 UIP; NATURAL8 reserved27; NATURAL8 reserved28; NATURAL8 reserved29; NATURAL8 UOP1; NATURAL8 reserved30; NATURAL8 reserved31; NATURAL8 reserved32; NATURAL8 UOP0;} MCF5206_UART2;#define MCF5206_UART_UMR1_RXRTS (0x80)#define MCF5206_UART_UMR1_RXIRQ (0x40)#define MCF5206_UART_UMR1_ERR (0x20)#define MCF5206_UART_UMR1_PM_MULTI_ADDR (0x1C)#define MCF5206_UART_UMR1_PM_MULTI_DATA (0x18)#define MCF5206_UART_UMR1_PM_NONE (0x10)#define MCF5206_UART_UMR1_PM_FORCE_HI (0x0C)#define MCF5206_UART_UMR1_PM_FORCE_LO (0x08)#define MCF5206_UART_UMR1_PM_ODD (0x04)#define MCF5206_UART_UMR1_PM_EVEN (0x00)#define MCF5206_UART_UMR1_BC_5 (0x00)#define MCF5206_UART_UMR1_BC_6 (0x01)#define MCF5206_UART_UMR1_BC_7 (0x02)#define MCF5206_UART_UMR1_BC_8 (0x03)#define MCF5206_UART_UMR2_CM_NORMAL (0x00)#define MCF5206_UART_UMR2_CM_ECHO (0x40)#define MCF5206_UART_UMR2_CM_LOCAL_LOOP (0x80)#define MCF5206_UART_UMR2_CM_REMOTE_LOOP (0xC0)#define MCF5206_UART_UMR2_TXRTS (0x20)#define MCF5206_UART_UMR2_TXCTS (0x10)#define MCF5206_UART_UMR2_STOP_BITS_1 (0x07)#define MCF5206_UART_UMR2_STOP_BITS_15 (0x08)#define MCF5206_UART_UMR2_STOP_BITS_2 (0x0F)#define MCF5206_UART_USR_RB (0x80)#define MCF5206_UART_USR_FE (0x40)#define MCF5206_UART_USR_PE (0x20)#define MCF5206_UART_USR_OE (0x10)#define MCF5206_UART_USR_TXEMP (0x08)#define MCF5206_UART_USR_TXRDY (0x04)#define MCF5206_UART_USR_FFULL (0x02)#define MCF5206_UART_USR_RXRDY (0x01)#define MCF5206_UART_UCSR_9600_BPS (0xBB)#define MCF5206_UART_UCSR_19200_BPS (0xCC)#define MCF5206_UART_UCR_NONE (0x00)#define MCF5206_UART_UCR_STOP_BREAK (0x70)#define MCF5206_UART_UCR_START_BREAK (0x60)#define MCF5206_UART_UCR_RESET_BKCHGINT (0x50)#define MCF5206_UART_UCR_RESET_ERROR (0x40)#define MCF5206_UART_UCR_RESET_TX (0x30)#define MCF5206_UART_UCR_RESET_RX (0x20)#define MCF5206_UART_UCR_RESET_MR (0x10)#define MCF5206_UART_UCR_TX_DISABLED (0x08)#define MCF5206_UART_UCR_TX_ENABLED (0x04)#define MCF5206_UART_UCR_RX_DISABLED (0x02)#define MCF5206_UART_UCR_RX_ENABLED (0x01)#define MCF5206_UART_UIPCR_COS (0x10)#define MCF5206_UART_UIPCR_CTS (0x01)#define MCF5206_UART_UACR_BRG (0x80)#define MCF5206_UART_UACR_CTMS_TIMER (0x60)#define MCF5206_UART_UACR_IEC (0x01)#define MCF5206_UART_UISR_COS (0x80)#define MCF5206_UART_UISR_DB (0x04)#define MCF5206_UART_UISR_RXRDY (0x02)#define MCF5206_UART_UISR_TXRDY (0x01)#define MCF5206_UART_UIMR_COS (0x80)#define MCF5206_UART_UIMR_DB (0x04)#define MCF5206_UART_UIMR_FFULL (0x02)#define MCF5206_UART_UIMR_TXRDY (0x01)typedef volatile struct{ NATURAL8 reserved1[0x1E0]; NATURAL8 MADR; NATURAL8 reserved2; NATURAL8 reserved3; NATURAL8 reserved4; NATURAL8 MFDR; NATURAL8 reserved5; NATURAL8 reserved6; NATURAL8 reserved7; NATURAL8 MBCR; NATURAL8 reserved8; NATURAL8 reserved9; NATURAL8 reserved10; NATURAL8 MBSR; NATURAL8 reserved11; NATURAL8 reserved12; NATURAL8 reserved13; NATURAL8 MBDR;} MCF5206_MBUS;#define MCF5206_MBUS_MADR_ADDR(a) ((a)&0xFE)#define MCF5206_MBUS_MFDR_MBC(a) ((a)&0x3F)#define MCF5206_MBUS_MBCR_MEN (0x80)#define MCF5206_MBUS_MBCR_MIEN (0x40)#define MCF5206_MBUS_MBCR_MSTA (0x20)#define MCF5206_MBUS_MBCR_MTX (0x10)#define MCF5206_MBUS_MBCR_TXAK (0x08)#define MCF5206_MBUS_MBCR_RSTA (0x04)#define MCF5206_MBUS_MBSR_MCF (0x80)#define MCF5206_MBUS_MBSR_MAAS (0x40)#define MCF5206_MBUS_MBSR_MBB (0x20)#define MCF5206_MBUS_MBSR_MAL (0x10)#define MCF5206_MBUS_MBSR_SRW (0x04)#define MCF5206_MBUS_MBSR_MIF (0x02)#define MCF5206_MBUS_MBSR_RXAK (0x01)/* Here we put the modules together. An example access for the UART mode * register would be: (assuming we have a pointer to the IMM): * imm->uart1.UMR */typedef volatile union{ MCF5206_SIM sim; MCF5206_GPIO gpio; MCF5206_UART1 uart1; MCF5206_UART2 uart2; MCF5206_TIMER timer; MCF5206_CS cs; MCF5206_DRAMC dramc; MCF5206_MBUS mbus;} MCF5206_IMM;#define IMM ((MCF5206_IMM *)(0xf0000000))/* Function prototypes */voidmcf5206_write_cacr (NATURAL32);voidmcf5206_write_acr0 (NATURAL32);voidmcf5206_write_acr1 (NATURAL32);voidmcf5206_write_vbr (NATURAL32);voidmcf5206_write_srambar (NATURAL32);voidmcf5206_write_mbar (NATURAL32);⌨️ 快捷键说明
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