📄 ocpuio.h
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/***************************************************************//* MCF5206 Eval Board by Arnewsh *//***************************************************************/#define DEFAULT_BAUD_RATE 57600#define CPU_CLOCK_FREQUENCY 25000000 /* Clock = 25Mhz */#define MCF5200#define MCF5206#define MYPRINTF#define NETWORK#define SYMBOL_MATCH_MASK (0xFFFFFFFF)#define FLASH_ADDRESS (0xFFE00000)#define DRAM_ADDRESS (0x00000000)#define IMM_ADDRESS (0x10000000)#define SRAM_ADDRESS (0x20000000)#define MC68HC901_ADDRESS (0x30000000)#define MC68HC901_IRQ (0xF0)#define ISA_ADDRESS (0x40000000)/* Macro which returns a pointer to the Internal Memory Map */ #define mcf5206_get_immp() ((MCF5206_IMM *)(IMM_ADDRESS))void ird (int, char **);void irm (int, char **);/* Defintions of the basic data types. */typedef unsigned char BYTE; /* 8 bits */typedef unsigned short int WORD; /* 16 bits */typedef unsigned long int LONG; /* 32 bits */typedef signed char SBYTE; /* 8 bits */typedef signed short int SWORD; /* 16 bits */typedef signed long int SLONG; /* 32 bits */typedef unsigned char NATURAL8; /* 8 bits */typedef unsigned short int NATURAL16; /* 16 bits */typedef unsigned long int NATURAL32; /* 32 bits */typedef signed char INTEGER8; /* 8 bits */typedef signed short int INTEGER16; /* 16 bits */typedef signed long int INTEGER32; /* 32 bits */#define ILLEGAL 0x4AFC /* 68K illegal instruction *//* * Definition of registers of the MCF5206. Note that not all * the registers accessible on the MCF5206 are actually listed * here. The reason for this is that not all registers on the * CPU are readable, thus it is up to the user to maintain a * readable/visible copy of the values contained in those * registers. */typedef struct{ /* Order IS VERY IMPORTANT -- MOVEM instruction */ NATURAL32 d0, d1, d2, d3, d4, d5, d6, d7; /* offset 00 04 08 12 16 20 24 28 */ NATURAL32 a0, a1, a2, a3, a4, a5, a6, a7; /* offset 32 36 40 44 48 52 56 60 */ NATURAL32 pc; /* offset 64 */ NATURAL16 sr; /* offset 68 */} REGISTERS;#define MCF5206_SR_T (0x8000)#define MCF5206_SR_S (0x2000)#define MCF5206_SR_M (0x1000)#define MCF5206_SR_IPL (0x0700)#define MCF5206_SR_X (0x0010)#define MCF5206_SR_N (0x0008)#define MCF5206_SR_Z (0x0004)#define MCF5206_SR_V (0x0002)#define MCF5206_SR_C (0x0001)/* Definition of what the single exception stack frame looks like. */typedef struct{ NATURAL16 form_vector; NATURAL16 status_register; NATURAL32 program_counter;} STACK_FRAME;#define SF_FORMAT(a) ((a->form_vector >> 12) & 0x00FF)#define SF_VECTOR(a) ((a->form_vector >> 2) & 0x00FF)#define SF_SR(a) (a->status_register)#define SF_PC(a) (a->program_counter)#define SF_FS(a) (((a->form_vector & 0x0C00)>>8) | (a->form_vector & 0x0003))/* Cache and Access Control Register routines and defintions */#define MCF5206_CACR_CENB (0x80000000)#define MCF5206_CACR_CFRZ (0x08000000)#define MCF5206_CACR_CINV (0x01000000)#define MCF5206_CACR_CMOD (0x00000200)#define MCF5206_CACR_CWRP (0x00000020)#define MCF5206_CACR_CLNF_00 (0x00000000)#define MCF5206_CACR_CLNF_01 (0x00000001)#define MCF5206_CACR_CLNF_10 (0x00000002)#define MCF5206_ACR_BASE(a) ((a)&0xFF000000)#define MCF5206_ACR_MASK(a) (((a)&0xFF000000) >> 8)#define MCF5206_ACR_EN (0x00008000)#define MCF5206_ACR_S_USER (0x00000000)#define MCF5206_ACR_S_SUPER (0x00002000)#define MCF5206_ACR_S_IGNORE (0x00006000)#define MCF5206_ACR_ENIB (0x00000080)#define MCF5206_ACR_CM (0x00000040)#define MCF5206_ACR_WP (0x00000004)#define MCF5206_SRAMBAR_BASE(a) ((a)&0xFFFFFE00)#define MCF5206_SRAMBAR_WP (0x00000100)#define MCF5206_SRAMBAR_AS_CI (0x00000080)#define MCF5206_SRAMBAR_AS_SC (0x00000040)#define MCF5206_SRAMBAR_AS_SD (0x00000020)#define MCF5206_SRAMBAR_AS_UC (0x00000004)#define MCF5206_SRAMBAR_AS_UD (0x00000002)#define MCF5206_SRAMBAR_V (0x00000001)#define MCF5206_MBAR_BASE(a) ((a)&0xFFFFFC00)#define MCF5206_MBAR_SC (0x00000010)#define MCF5206_MBAR_SD (0x00000008)#define MCF5206_MBAR_UC (0x00000004)#define MCF5206_MBAR_UD (0x00000002)#define MCF5206_MBAR_V (0x00000001)/* Memory-mapped System Integration registers */typedef volatile struct{ NATURAL8 reserved0; NATURAL8 reserved1; NATURAL8 reserved2; NATURAL8 SIMR; NATURAL32 reserved3; NATURAL32 reserved4; NATURAL32 reserved5; NATURAL32 reserved6; NATURAL8 ICR1; NATURAL8 ICR2; NATURAL8 ICR3; NATURAL8 ICR4; NATURAL8 ICR5; NATURAL8 ICR6; NATURAL8 ICR7; NATURAL8 ICR8; NATURAL8 ICR9; NATURAL8 ICR10; NATURAL8 ICR11; NATURAL8 ICR12; NATURAL8 ICR13; NATURAL8 reserved7; NATURAL8 reserved8; NATURAL8 reserved9; NATURAL32 reserved10[4]; NATURAL8 reserved11; NATURAL8 reserved12; NATURAL16 IMR; NATURAL16 reserved13; NATURAL16 IPR; NATURAL32 reserved14; NATURAL8 RSR; NATURAL8 SYPCR; NATURAL8 SWIVR; NATURAL8 SWSR; NATURAL8 reserved31[135]; NATURAL8 PAR;} MCF5206_SIM;#define MCF5206_SIM_SIMR_FRZ1 (0x80)#define MCF5206_SIM_SIMR_FRZ0 (0x40)#define MCF5206_SIM_SIMR_BL (0x01)#define MCF5206_SIM_ICR_AVEC (0x80)#define MCF5206_SIM_ICR_IL(a) (((a)&0x07)<<2)#define MCF5206_SIM_ICR_IP(a) (((a)&0x03))#define MCF5206_SIM_IMR_UART2 (0x2000)#define MCF5206_SIM_IMR_UART1 (0x1000)#define MCF5206_SIM_IMR_MBUS (0x0800)#define MCF5206_SIM_IMR_T2 (0x0400)#define MCF5206_SIM_IMR_T1 (0x0200)#define MCF5206_SIM_IMR_SWT (0x0100)#define MCF5206_SIM_IMR_EINT7 (0x0080)#define MCF5206_SIM_IMR_EINT6 (0x0040)#define MCF5206_SIM_IMR_EINT5 (0x0020)#define MCF5206_SIM_IMR_EINT4 (0x0010)#define MCF5206_SIM_IMR_EINT3 (0x0008)#define MCF5206_SIM_IMR_EINT2 (0x0004)#define MCF5206_SIM_IMR_EINT1 (0x0002)#define MCF5206_SIM_IPR_UART2 (0x2000)#define MCF5206_SIM_IPR_UART1 (0x1000)#define MCF5206_SIM_IPR_MBUS (0x0800)#define MCF5206_SIM_IPR_T2 (0x0400)#define MCF5206_SIM_IPR_T1 (0x0200)#define MCF5206_SIM_IPR_SWT (0x0100)#define MCF5206_SIM_IPR_EINT7 (0x0080)#define MCF5206_SIM_IPR_EINT6 (0x0040)#define MCF5206_SIM_IPR_EINT5 (0x0020)#define MCF5206_SIM_IPR_EINT4 (0x0010)#define MCF5206_SIM_IPR_EINT3 (0x0008)#define MCF5206_SIM_IPR_EINT2 (0x0004)#define MCF5206_SIM_IPR_EINT1 (0x0002)#define MCF5206_SIM_RSR_HRST (0x80)#define MCF5206_SIM_RSR_SWTR (0x20)#define MCF5206_SIM_SYPCR_SWE (0x80)#define MCF5206_SIM_SYPCR_SWRI (0x40)#define MCF5206_SIM_SYPCR_SWT_2_9 (0x00)#define MCF5206_SIM_SYPCR_SWT_2_11 (0x08)#define MCF5206_SIM_SYPCR_SWT_2_13 (0x10)#define MCF5206_SIM_SYPCR_SWT_2_15 (0x18)#define MCF5206_SIM_SYPCR_SWT_2_18 (0x20)#define MCF5206_SIM_SYPCR_SWT_2_20 (0x28)#define MCF5206_SIM_SYPCR_SWT_2_22 (0x30)#define MCF5206_SIM_SYPCR_SWT_2_24 (0x38)#define MCF5206_SIM_SYPCR_BME (0x04)#define MCF5206_SIM_SYPCR_BM_1024 (0x00)#define MCF5206_SIM_SYPCR_BM_512 (0x01)#define MCF5206_SIM_SYPCR_BM_256 (0x02)#define MCF5206_SIM_SYPCR_BM_128 (0x03)#define MCF5206_SIM_SWIVR_SWIV(a) ((a)&0x00FF)#define MCF5206_SIM_PAR_PAR7 (0x80)#define MCF5206_SIM_PAR_PAR7_RSTO (0x00)#define MCF5206_SIM_PAR_PAR7_RTS2 (0x80)#define MCF5206_SIM_PAR_PAR6 (0x40)#define MCF5206_SIM_PAR_PAR6_IRQ (0x00)#define MCF5206_SIM_PAR_PAR6_IPL (0x40)#define MCF5206_SIM_PAR_PAR5 (0x20)#define MCF5206_SIM_PAR_PAR5_PP74 (0x00)#define MCF5206_SIM_PAR_PAR5_PST (0x20)#define MCF5206_SIM_PAR_PAR4 (0x10)#define MCF5206_SIM_PAR_PAR4_PP30 (0x00)#define MCF5206_SIM_PAR_PAR4_DDATA (0x10)#define MCF5206_SIM_PAR_PAR3 (0x08)#define MCF5206_SIM_PAR_PAR2 (0x04)#define MCF5206_SIM_PAR_PAR1 (0x02)#define MCF5206_SIM_PAR_PAR0 (0x01)typedef volatile struct{ NATURAL8 reserved0[0x1C5]; NATURAL8 PPDDR; NATURAL8 reserved34; NATURAL8 reserved35; NATURAL8 reserved36; NATURAL8 PPDAT;} MCF5206_GPIO;#define MCF5206_PP_PPDDR_DDR7_INPUT (~0x80)#define MCF5206_PP_PPDDR_DDR7_OUTPUT ( 0x80)#define MCF5206_PP_PPDDR_DDR6_INPUT (~0x40)#define MCF5206_PP_PPDDR_DDR6_OUTPUT ( 0x40)#define MCF5206_PP_PPDDR_DDR5_INPUT (~0x20)#define MCF5206_PP_PPDDR_DDR5_OUTPUT ( 0x20)#define MCF5206_PP_PPDDR_DDR4_INPUT (~0x10)#define MCF5206_PP_PPDDR_DDR4_OUTPUT ( 0x10)#define MCF5206_PP_PPDDR_DDR3_INPUT (~0x08)#define MCF5206_PP_PPDDR_DDR3_OUTPUT ( 0x08)#define MCF5206_PP_PPDDR_DDR2_INPUT (~0x04)#define MCF5206_PP_PPDDR_DDR2_OUTPUT ( 0x04)#define MCF5206_PP_PPDDR_DDR1_INPUT (~0x02)#define MCF5206_PP_PPDDR_DDR1_OUTPUT ( 0x02)#define MCF5206_PP_PPDDR_DDR0_INPUT (~0x01)#define MCF5206_PP_PPDDR_DDR0_OUTPUT ( 0x01)#define MCF5206_PP_PPDAT_DAT7 ( 0x80)#define MCF5206_PP_PPDAT_DAT6 ( 0x40)#define MCF5206_PP_PPDAT_DAT5 ( 0x20)#define MCF5206_PP_PPDAT_DAT4 ( 0x10)#define MCF5206_PP_PPDAT_DAT3 ( 0x08)#define MCF5206_PP_PPDAT_DAT2 ( 0x04)#define MCF5206_PP_PPDAT_DAT1 ( 0x02)#define MCF5206_PP_PPDAT_DAT0 ( 0x01)typedef volatile struct{ NATURAL32 reserved1[0x19]; NATURAL16 CSAR0; NATURAL16 rsvd0; NATURAL32 CSMR0; NATURAL16 reserved2; NATURAL16 CSCR0; NATURAL16 CSAR1; NATURAL16 rsvd1; NATURAL32 CSMR1; NATURAL16 reserved4; NATURAL16 CSCR1; NATURAL16 CSAR2; NATURAL16 rsvd2; NATURAL32 CSMR2; NATURAL16 reserved6; NATURAL16 CSCR2; NATURAL16 CSAR3; NATURAL16 rsvd3; NATURAL32 CSMR3; NATURAL16 reserved8; NATURAL16 CSCR3; NATURAL16 CSAR4; NATURAL16 rsvd4; NATURAL32 CSMR4; NATURAL16 reserved10; NATURAL16 CSCR4; NATURAL16 CSAR5; NATURAL16 rsvd5; NATURAL32 CSMR5; NATURAL16 reserved12; NATURAL16 CSCR5; NATURAL16 CSAR6; NATURAL16 rsvd6; NATURAL32 CSMR6; NATURAL16 reserved14; NATURAL16 CSCR6; NATURAL16 CSAR7; NATURAL16 rsvd7; NATURAL32 CSMR7; NATURAL16 reserved16; NATURAL16 CSCR7; NATURAL16 reserved17; NATURAL16 DMCR;} MCF5206_CS;#define MCF5206_CS_CSAR_BASE(a) (((a)&0xFFFF0000)>>16)#define MCF5206_CS_CSMR_MASK_32M (0x01FF0000)#define MCF5206_CS_CSMR_MASK_16M (0x00FF0000)#define MCF5206_CS_CSMR_MASK_8M (0x007F0000)#define MCF5206_CS_CSMR_MASK_4M (0x003F0000)#define MCF5206_CS_CSMR_MASK_2M (0x001F0000)#define MCF5206_CS_CSMR_MASK_1M (0x000F0000)#define MCF5206_CS_CSMR_MASK_1024K (0x000F0000)#define MCF5206_CS_CSMR_MASK_512K (0x00070000)#define MCF5206_CS_CSMR_MASK_256K (0x00030000)#define MCF5206_CS_CSMR_MASK_128K (0x00010000)#define MCF5206_CS_CSMR_MASK_64K (0x00000000)#define MCF5206_CS_CSMR_SC (0x00000010)#define MCF5206_CS_CSMR_SD (0x00000008)#define MCF5206_CS_CSMR_UC (0x00000004)#define MCF5206_CS_CSMR_UD (0x00000002)#define MCF5206_CS_CSMR1_CPU (0x00000020)#define MCF5206_CS_CSCR_WS_MASK (0x3C00)#define MCF5206_CS_CSCR_WS(a) (((a)&0x0F)<<10)#define MCF5206_CS_CSCR_BRST (0x0200)#define MCF5206_CS_CSCR_AA (0x0100)#define MCF5206_CS_CSCR_PS_8 (0x0040)#define MCF5206_CS_CSCR_PS_16 (0x0080)#define MCF5206_CS_CSCR_PS_32 (0x0000)#define MCF5206_CS_CSCR_EMAA (0x0020)#define MCF5206_CS_CSCR_ASET (0x0010)#define MCF5206_CS_CSCR_WRAH (0x0008)#define MCF5206_CS_CSCR_RDAH (0x0004)#define MCF5206_CS_CSCR_WR (0x0002)#define MCF5206_CS_CSCR_RD (0x0001)#define MCF5206_CS_DMCR_WS_MASK (0x3C00)#define MCF5206_CS_DMCR_WS(a) (((a)&0x0F)<<10)#define MCF5206_CS_DMCR_BRST (0x0200)⌨️ 快捷键说明
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