reset.s

完整的Bell实验室的嵌入式文件系统TFS

    bl      put_string

..dead:
    b       ..dead

/* Ram check failure string. */

..dfail_string:
    .byte "Data area failed RW test!! "
    .byte 0x0d,0x0a,0x00
    .align 2
..fail_addr:
    .byte "Failing Address:  "
    .align 2
..fail_testval:
    .byte "Expected : "
    .align 2
..fail_actual:
    .byte "Actual   : "
    .align 2
..newline:
    .byte 0x0d,0x0a,0x00
    .align 2

/****************************************************************************
 *
 * Function:     iic0_init
 * Description:  Initializes IIC0 for use of IIC bus during memory
 *               configuration.
 */
    .text
    .align 2
    .globl  iic0_init

iic0_init:
    /*
     * Initialize IIC0 controller.
     */
    addis   r3,0,IIC0_BASE@h        /* r3 <-base addr of IIC0 cntrlr */
    ori     r3,r3,IIC0_BASE@l
    addi    r4,0,0x00
    stb     r4,IICLMADR(r3)         /* clear lo master address */
    eieio
    stb     r4,IICHMADR(r3)         /* clear hi master address */
    eieio
    stb     r4,IICLSADR(r3)         /* clear lo slave address */
    eieio
    stb     r4,IICHSADR(r3)         /* clear hi slave address */
    eieio
    addi    r4,0,0x08
    stb     r4,IICSTS(r3)           /* clear status */
    eieio
    addi    r4,0,0x8F
    stb     r4,IICEXTSTS(r3)        /* clear extended status */
    eieio
    addi    r4,0,0x03               /* set clock divisor */
    stb     r4,IICCLKDIV(r3)        /* OPB 30-40Mhz => 3 */
    eieio                           /* OPB 40-50Mhz => 4 */
    addi    r4,0,0x00
    stb     r4,IICINTRMSK(r3)       /* no interrupts */
    eieio
    stb     r4,IICXFRCNT(r3)        /* clear transfer count */
    eieio
    addi    r4,0,0xF0
    stb     r4,IICXTCNTLSS(r3)      /* clear extended control & stat */
    eieio
    addi    r4,0,0x43               /* set mode control - flush */
    stb     r4,IICMDCNTL(r3)        /* master data buf, enable hold */
    eieio                           /* SCL, exit unknown state */
    addi    r4,0,0x00
    stb     r4,IICCNTL(r3)          /* clear control reg */
    eieio

    blr

/****************************************************************************
 *
 * Function:     iic0_read
 * Description:  Does a one byte read from the SDRAM EEPROM via IIC0 bus.
 *               You must do a one byte write to the device addr with the
 *               device subaddress to be read before doing a read.
 *      The SDRAM EEPROM IIC device address is 0xA1 for read and   
 *               and 0xA0 for write.      
 * Input: r3 = device subaddress of byte to be read from SDRAM EEPROM
 * Output r3 = byte value of device subaddress read
 */
    .text
    .align 2
    .globl  iic0_read

    /*
     * iic_read routine - does 1 byte read from SDRAM EEPROM on IIC0 bus.
     * iic combined format read requires a write of the byte we want to
     * read, before doing the read.
     */
iic0_read:
    addis   r10,0,IIC0_BASE@h       /* r10 <-base addr of IIC0 cntrlr */
    ori     r10,r10,IIC0_BASE@l 

    addi    r11,0,0x08              /* clear status */
    stb     r11,IICSTS(r10)
    eieio

    addis   r12,r0,0x0001           /* set up counter for timeout */
    mtctr   r12
..chk_sts1:
    lbz     r11,IICSTS(r10)         /* read status */
    eieio
    andi.   r11,r11,0x01            /* check for pending transfer */
    beq     ..sts_ok1               /* if 0, OK */
    bdnz    ..chk_sts1
    /*
     * If we get here, we timed out on clear status
     */
    addis   r3,r0,..iic0_timeout_fail@h
    ori     r3,r3,..iic0_timeout_fail@l
    bl      put_string
..iic0_timeout_fail_spin:
    b       ..iic0_timeout_fail_spin/* halt - can not clear status */
..sts_ok1:
    lbz     r11,IICMDCNTL(r10)      /* read mode control */
    eieio
    ori     r11,r11,0x40            /* flush master data buffer */
    stb     r11,IICMDCNTL(r10)
    eieio
    addi    r11,0,0xA0              /* set device address for */
    stb     r11,IICLMADR(r10)       /* SDRAM EEPROM write (0xA0) */
    eieio
    stb     r3,IICMDBUF(r10)        /* set device sub address */
                                    /* which is the byte # to read */
    addi    r11,0,0x01              /* start write of 1 byte */
    stb     r11,IICCNTL(r10)
    eieio

    addis   r12,r0,0x0001           /* set up counter for timeout */
    mtctr   r12
..chk_sts2:
    lbz     r11,IICSTS(r10)         /* read status */
    eieio
    andi.   r11,r11,0x01            /* check for pending transfer */
    beq     ..write_ok              /* if 0, OK */
    bdnz    ..chk_sts2
    /*
     * If we get here, we timed out on writing the SDRAM EEPROM
     * Could be No DIMM. Halt since memory can not be configured
     * properly without the EEPROM data.
     */
    addis   r3,r0,..iic0_read_fail@h
    ori     r3,r3,..iic0_read_fail@l
    bl      put_string
..iic0_read_fail_spin:
    b       ..iic0_read_fail_spin   /* halt - read failed */
..write_ok:
    addi    r11,0,0x08              /* clear status */
    stb     r11,IICSTS(r10)
    eieio

    addis   r12,r0,0x0001           /* set up counter for timeout */
    mtctr   r12
..chk_sts3:
    lbz     r11,IICSTS(r10)         /* read status */
    eieio
    andi.   r11,r11,0x01            /* check for pending transfer */
    beq     ..sts_ok2               /* if 0, OK */
    bdnz    ..chk_sts3
    /*
     * If we get here, we timed out on clear status
     */
    addis   r3,r0,..iic0_timeout_fail@h
    ori     r3,r3,..iic0_timeout_fail@l
    bl      put_string
    b       ..iic0_timeout_fail_spin/* halt - can not clear status */
..sts_ok2:
    lbz     r11,IICMDCNTL(r10)      /* read mode control */
    eieio
    ori     r11,r11,0x40            /* flush master data buffer */
    stb     r11,IICMDCNTL(r10)
    eieio
    addi    r11,0,0xA1              /* set device address for */
    stb     r11,IICLMADR(r10)       /* SDRAM EEPROM (0xA1) */
    eieio
    addi    r11,0,0x03              /* read of 1 byte */
    stb     r11,IICCNTL(r10)
    eieio

    addis   r12,r0,0x0001           /* set up counter for timeout */
    mtctr   r12
..chk_sts4:
    lbz     r11,IICSTS(r10)         /* read status */
    eieio
    andi.   r11,r11,0x01            /* check for pending transfer */
    beq     ..read_ok               /* if 0, OK */
    bdnz    ..chk_sts4
    /*
     * If we get here, we timed out on reading the SDRAM EEPROM
     * Could be No DIMM. Halt since memory can not be configured
     * properly without the EEPROM data.
     */
    addis   r3,r0,..iic0_read_fail@h
    ori     r3,r3,..iic0_read_fail@l
    bl      put_string
    b       ..iic0_read_fail_spin   /* halt - read failed */
..read_ok:
    lbz     r3,IICMDBUF(r10)        /* read byte returned from EEPROM */
    eieio

    blr                             /* return with data in R3 */

/*****************************************************************************
 *
 * Function: prt_word
 * Take reg 3 and spit it out in hex.
 */
    .global putmsrtest
    .global msrshow
putmsrtest:
    addis   r3,r0,0x1000        /* set ME bit (Machine Exceptions) */
    oris    r3,r3,0x0002        /* set CE bit (Critical Exceptions) */
    mtmsr   r3                  /* change MSR */
    blr

msrshow:
    mfmsr   r3

prt_word:
    mflr    r31
    addi    r18,r3,0x0000       /* save in r18 */
    addi    r4,r0,0x8           /* load count in r4 */
    mtctr   r4
..wrdlp:
    rlwinm  r3,r18,4,0xF        /* isolate ls nibble of r18 */
    cmpi    cr0,0,r3,0x9
    addi    r3,r3,0x30
    bgt     ..alpha
    /* A regular number here, add 0x30. */
    b       ..jn
..alpha:
    /* A hex char, add 0x7. */
    addi    r3, r3, 0x7
..jn:
    bl      s1putchar
    rlwinm  r18,r18,4,0xFFFFFFFF
    bdnz    ..wrdlp
    mtlr    r31
    blr


/*****************************************************************************
 *
 * Function: put_string
 * Puts a string pointed to by r3 out on com1.
 */
put_string:
    mflr    r31
    addi    r17,r3,0x0
..pdt_loop:
    lbz     r3,0x0(r17)         /* pull byte */
    cmpi    cr0,0,r3,0x0        /* compare against null string */
    beq     ..dout
    bl      s1putchar           /* output character */
    addi    r17,r17,0x1
    b       ..pdt_loop
..dout:
    mtlr    r31
    blr

#if INCLUDE_HERALD
..herald_GP:
    .byte 0x0d,0x0a
    .byte "405GP Starting up..."
    .byte 0x0d,0x0a,0x00
    .align 2
#endif

#if INCLUDE_ECC
..sdram_start:
    .byte "SDRAM Initialization from EEPROM..."
    .byte "(this takes about a minute!)"
    .byte 0x0d,0x0a,0x00
    .align 2
#endif

/*
 * IIC0 read failure from SDRAM EEPROM.
 */
..iic0_read_fail:
    .byte 0x0d,0x0a,0x0d,0x0a
    .byte "HALTED !!!"
    .byte 0x0d,0x0a
    .byte "IIC0 Read Error from SDRAM EEPROM!"
    .byte 0x0d,0x0a
    .byte "Ensure DIMM is plugged properly!"
    .byte 0x0d,0x0a,0x00
    .align 2
/*
 * IIC0 clear status failure.
 */
..iic0_timeout_fail:
    .byte 0x0d,0x0a,0x0d,0x0a
    .byte "HALTED !!! IIC0 Failure - Timeout due to pending transfer !"
    .byte "                        - Could not clear status reg !"
    .byte 0x0d,0x0a
    .byte "Ensure DIMM is plugged properly!"
    .byte 0x0d,0x0a,0x00
    .align 2
/*
 * Invalid DIMM mode read from EEPROM
 */
..invalid_dimm_mode:
    .byte 0x0d,0x0a,0x0d,0x0a
    .byte "HALTED !!! Invalid DIMM mode read from SDRAM EEPROM!"
    .byte 0x0d,0x0a
    .byte "Ensure DIMM is plugged properly!"
    .byte 0x0d,0x0a
    .byte "Note: byte 1 #rows, byte 2 #cols, byte 3 #internal banks"
    .byte 0x0d,0x0a
    .byte "Value read :  "
    .byte 0x00
    .align 2


/*****************************************************************************
 *
 * Function: uart0_init
 * uart0_init():
 */
#define UART0_BASE 0xef600300
#define DATA_REG        0x00    
#define DL_LSB          0x00    
#define DL_MSB          0x01
#define INT_ENABLE      0x01
#define FIFO_CONTROL    0x02 
#define LINE_CONTROL    0x03
#define MODEM_CONTROL   0x04
#define LINE_STATUS     0x05
#define MODEM_STATUS    0x06
#define SCRATCH         0x07

    .text
    .align  2
    .globl  async_init
uart0_init:
    addis   r7,r0,UART0_BASE@h      /* set base addr for UART0 */
    ori     r7,r7,UART0_BASE@l
    addi    r3,r0,0x80              /* set DLAB bit */
    stb     r3,LINE_CONTROL(r7)
    addi    r3,r0,0x24              /* set divisors for 19200 baud */
    stb     r3,DL_LSB(r7)
    addi    r3,r0,0x00
    stb     r3,DL_MSB(r7)
    addi    r3,r0,0x03              /* line control 8 bits no parity */
    stb     r3,LINE_CONTROL(r7)
    addi    r3,r0,0x00              /* disable FIFO */
    stb     r3,FIFO_CONTROL(r7)
    addi    r3,r0,0x03              /* modem control DTR RTS */
    stb     r3,MODEM_CONTROL(r7)
    lbz     r4,LINE_STATUS(r7)      /* clear line status */
    lbz     r4,DATA_REG(r7)         /* read receive buffer */
    addi    r3,r0,0x00              /* set scratchpad */
    stb     r3,SCRATCH(r7)
    addi    r3,r0,0x00              /* set interrupt enable reg */
    stb     r3,INT_ENABLE(r7)
    blr

/*
 * Function:     s1putchar
 * Description:  Put a character out on UART0
 */
    .text
    .align  2
    .globl  s1putchar
s1putchar:
    mfmsr   r8
    addi    r9,0,0x7FFF             /* Mask external interrupts */
    oris    r9,r9,0xFFFF
    and     r9,r9,r8
    mtmsr   r9
    addis   r7,r0,UART0_BASE@h      /* set base address for UART0 */
    ori     r7,r7,UART0_BASE@l  
    stb     r3,DATA_REG(r7)         /* put character out */
    eieio
..spnlp:
    lbz     r4,LINE_STATUS(r7)
    eieio
    andi.   r4,r4,0x20              /* check for THRE bit */
    beq     ..spnlp
    mtmsr   r8                      /* restore interrupts */
    blr