reset.s

完整的Bell实验室的嵌入式文件系统TFS

    ori     r14,r14,0x0A04
    cmp     0,0,r4,r14          /* 13x10(4) */
    beq     ..mode3
    addis   r14,0,0x0D
    ori     r14,r14,0x0B04
    cmp     0,0,r4,r14          /* 13x11(4) */
    beq     ..mode3
    addis   r14,0,0x0C
    ori     r14,r14,0x0804
    cmp     0,0,r4,r14          /* 12x8(4) */
    beq     ..mode4
    addis   r14,0,0x0C
    ori     r14,r14,0x0802
    cmp     0,0,r4,r14          /* 12x8(2) */
    beq     ..mode4
    addis   r14,0,0x0B
    ori     r14,r14,0x0802
    cmp     0,0,r4,r14          /* 11x8(2) */
    beq     ..mode5
    addis   r14,0,0x0B
    ori     r14,r14,0x0804
    cmp     0,0,r4,r14          /* 11x8(4) */
    beq     ..mode5
    addis   r14,0,0x0D
    ori     r14,r14,0x0802
    cmp     0,0,r4,r14          /* 13x8(2) */
    beq     ..mode6
    addis   r14,0,0x0D
    ori     r14,r14,0x0804
    cmp     0,0,r4,r14          /* 13x8(4) */
    beq     ..mode6
    addis   r14,0,0x0D
    ori     r14,r14,0x0902
    cmp     0,0,r4,r14          /* 13x9(2) */
    beq     ..mode7
    addis   r14,0,0x0D
    ori     r14,r14,0x0A02
    cmp     0,0,r4,r14          /* 13x10(2) */
    beq     ..mode7
    /*
     * If we get here, then mode bytes read are invalid
     */
    addis   r3,r0,..invalid_dimm_mode@h
    ori     r3,r3,..invalid_dimm_mode@l
    or      r14,r4,r4                   /* save r4 in r14 since call */
    bl      put_string                  /* to put_string uses r4 */
    or      r3,r14,r14                  /* put mode read into r3 */
    bl      prt_word                    /* print our mode values read */
..invalid_dimm_mode_spin:
    b       ..invalid_dimm_mode_spin    /* halt - invalid dimm mode */
    /*
     * Store mode bit values in r4. We will use this value when 
     * setting the SDx_AM field (bits 16:18 of the MBxCF regs)
     * for each of the SDRAM banks. 
     */
..mode7:
    addi    r4,0,0x6
    b       ..mode_set
..mode6:
    addi    r4,0,0x5
    b       ..mode_set
..mode5:
    addi    r4,0,0x4
    b       ..mode_set
..mode4:
    addi    r4,0,0x3
    b       ..mode_set
..mode3:
    addi    r4,0,0x2
    b       ..mode_set
..mode2:
    addi    r4,0,0x1
    b       ..mode_set
..mode1:
    addi    r4,0,0x0
..mode_set:
    /*
     * Determine the size of each bank by using the Module Bank Density
     * value stored in r7 as read from the SDRAM DIMM EEPROM. Since 
     * the value currently in r7 contains the size per 64-bit
     * bank on the DIMM, we divide this value by 2 (shift right 1 bit)
     * to determine the size per 32-bit bank.
     */
    srwi    r7,r7,1         /* calc size per 32 bit bank */
    cmpi    0,0,r7,0x02     /* check r7 for bank size */
    beq     ..meg8          /* and use value to calc bank end addr */
    cmpi    0,0,r7,0x04
    beq     ..meg16
    cmpi    0,0,r7,0x08
    beq     ..meg32
    cmpi    0,0,r7,0x10
    beq     ..meg64 
    cmpi    0,0,r7,0x20
    beq     ..meg128
    addi    r7,0,0x100      /* must be 256M */
    addi    r8,0,0x6        /* set size bits (SDx_SZ) for MBxCF reg */
    b       ..set_mb
..meg8:
    addi    r7,0,0x08         
    addi    r8,0,0x1        /* set size bits (SDx_SZ) for MBxCF reg */
    b       ..set_mb
..meg16:
    addi    r7,0,0x10        
    addi    r8,0,0x2        /* set size bits (SDx_SZ) for MBxCF reg */
    b       ..set_mb
..meg32:
    addi    r7,0,0x20       
    addi    r8,0,0x3        /* set size bits (SDx_SZ) for MBxCF reg */
    b       ..set_mb
..meg64:
    addi    r7,0,0x40      
    addi    r8,0,0x4        /* set size bits (SDx_SZ) for MBxCF reg */
    b       ..set_mb
..meg128:
    addi    r7,0,0x80     
    addi    r8,0,0x5        /* set size bits (SDx_SZ) for MBxCF reg */

..set_mb:
    /*
     * Set the SDRAM memory configuration regs (MBxCF). To do this we must
     * first determine the number of 32-bit banks to be configured. Note 
     * that the number of banks in r5 is the number of 64-bit banks as 
     * read from the SDRAM DIMM EEPROM. Since the 405GP only supports
     * 32-bit memory, each 64-bit bank must be configured as 2 separate
     * 32-bit banks. We also use the address mode stored in r4, the 
     * size per 32-bit bank stored in r7, and the bank size bits stored
     * in r8 to configure the SDRAM memory bank regsisters (MBxCF).
     * Note that Memory starts at address 0x00000000 and
     * continues contiguously.
     */
    rlwinm  r4,r4,13,0xFFFFFFFF /* set SDx_AM (addr mode field bits */
                                /* 16:18) to be used when setting */
                                /* MBxCF regs */
    rlwinm  r8,r8,17,0xFFFFFFFF /* set SDx_SZ (size field bits */
                                /* 12:14) to be used when setting */
                                /* MBxCF regs */
    or  r4,r4,r8                /* set SDx_AM and SDx_SZ fields - these */
                                /* settings are the same for all  */
                                /* SDRAM banks since only 1 DIMM */
    ori     r4,r4,0x1           /* set SDx_BE bit (bank enable)  */
    rlwinm  r7,r7,20,0xFFFFFFFF /* set up r7 (size per bank) to be used */
                                /* for calculating the SDx_BA field */
                                /* (base addr field bits 0:9) */
                                /* when setting the MBxCF regs */


    /*
     * Set MB0CF for bank 0. No need to add r7 for bank 0 since base
     * address for MB0CF is 0x00000000.  
     */
    addi    r2,0,mem_mb0cf
    mtdcr   memcfga,r2
    mtdcr   memcfgd,r4

    /*
     * Set MB2CF for bank 2.
     */
    addi    r2,0,mem_mb2cf
    mtdcr   memcfga,r2
    add r4,r4,r7        /* set base address for this bank  */
                        /* by adding bank size to SDx_SZ field */
    mtdcr   memcfgd,r4

    /*
     * Check r5 which contains the # of 64-bit banks as read from the 
     * SDRAM DIMM EEPROM, to determine if SDRAM banks 1 and 3 need
     * to be configured as well.
     */
    cmpi    0,0,r5,0x2  /* check # of 64-bit banks in r5 */
                        /* if 2 then banks MB2CF and MB3CF  */
                        /* also need to be configured */
    bne     ..mb_set

..banks2_3:
    /*
     * Set MB1CF for bank 1.
     */
    addi    r2,0,mem_mb1cf
    mtdcr   memcfga,r2
    add     r4,r4,r7    /* set base address for this bank */
                        /* by adding bank size to SDx_SZ field */
    mtdcr   memcfgd,r4
    /*
     * Set MB3CF for bank 3.
     */
    addi    r2,0,mem_mb3cf
    mtdcr   memcfga,r2
    add     r4,r4,r7    /* set base address for this bank */
                        /* by adding bank size to SDx_SZ field */
    mtdcr   memcfgd,r4

..mb_set:
    /*
     * Take defaults for SDRAM Timing reg, SDTR1.
     */

    /*
     * Check bank width value in r6 to determine if ECC is possible 
     * with the SDRAM being used. The Walnut board provides up to four
     * 32-bit banks of SDRAM, of which only bank 0 and 
     * bank 1 can support ECC since a 64-bit DIMM is being used. 
     * Banks 2 and 3 can still be used as non-ECC memory provided   
     * ECC correction is disabled for those banks. 
     * 
     * NOTE: If ECC SDRAM is being used, ECC correction should be enabled
     * only after the portion of the ECC SDRAM memory to be used has been
     * initialized with ECC enabled (MCOPT1 MEMCHK bits). That portion of
     * memory must be initialized with ECC enabled but with correction
     * disabled to ensure the correct ECC checkbits get stored properly. 
     * Since ECC does read-modify-writes, if correction was enabled 
     * before initilaizing memory with ECC enabled, the checkbits returned
     * on the read would be garbage and would trigger an ECC error.
     */
#if INCLUDE_ECC
    cmpi    0,0,r6,0x40     /* Check bank width, if 0x40 then */
    beq     ..no_ecc        /* 64 bit and no ECC, else assume ECC */
    addis   r9,0,0x9080     /* set value to program the MCOPT1  */
    ori     r9,r9,0x0000    /* reg; DC_EN=1, MEMCHK='10' to    */
    b   ..cont1             /* enable ECC, and BRD_PRF to '01' */
                            /* for 16 byte PLB burst read/prefetch   */
#endif
..no_ecc:
    addis   r9,0,0x8080     /* set value to program the MCOPT1 */
    ori     r9,r9,0x0000    /* reg; DC_EN=1, MEMCHK='00' to */
                            /* disable ECC, and BRD_PRF to '01' */
                            /* for 16 byte PLB burst read/prefetch */
..cont1:
    /*
     * Delay to ensure 200usec have elapsed since reset. Assume worst
     * case that the core is running 200Mhz:
     *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
     */
    addis   r3,0,0x0000
    ori     r3,r3,0xA000    /* ensure 200usec have passed since reset */
    mtctr   r3
..spinlp2:
    bdnz    ..spinlp2       /* spin loop */

    /*
     * Set memory controller options reg, MCOPT1 with value in r9.
     * This enables the SDRAM controller. 
     */
    addi    r2,0,mem_mcopt1
    mtdcr   memcfga,r2
    mtdcr   memcfgd,r9

    /*
     * Delay to ensure 10msec have elapsed since reset. This is 
     * required for the MPC952 to stabalize. Assume worst
     * case that the core is running 200Mhz:
     *   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
     * This delay should occur before accessing SDRAM.
     */
    addis   r3,0,0x001E
    ori     r3,r3,0x8480    /* ensure 10msec have passed since reset */
    mtctr   r3
..spinlp3:
    bdnz    ..spinlp3       /* spin loop */


    /*
     * Check value in r9 to see if ECC was enabled in MCOPT1 reg..
     * Bit 3 of the MCOPT1 MEMCHK field can be used to determine if 
     * ECC enabled.
     */
    rlwinm. r9,r9,0,0x10000000  /* Check MEMCHK bit 3 of MCOPT1 */
    beq     ..ecc_disabled

..ecc_enabled:
    /*
     * Now that SDRAM memory is enabled, initialize its entire
     * address range by writing it with zeros. This is necessary when
     * using ECC SDRAM since the memory must be initialized with ECC
     * enabled to ensure the checkbits get initialized correctly.
     * This must occur BEFORE enabling ECC correction. Otherwise, since
     * ECC performs read-modify writes, the checkbits returned on the
     * read would be garbage and an ECC error flagged. ECC correction
     * should only be enabled after initializing the ECC memory space
     * with ECC enabled.
     */
    add     r4,r4,r7            /* use last MBxCF reg setting still */
                                /* in r4 and the bank size still in r7 */
                                /* to calculate the total size of */
                                /* SDRAM memory; here we add the bank */
                                /* size to the last bank base addr */
                                /* to determine the amount of SDRAM */
    rlwinm   r4,r4,0,0xFFC00000 /* mask off all but the base addr field */
                                /* and this value is the final SDRAM */
                                /* address */
    addis   r3,r0,0xFFFF        /* set r3 to start address (used */
    ori     r3,r3,0xFFF8        /* to start at addr 0x00000000) */
    addis   r6,r0,0xFFFF        /* set r6 to start address (used */
    ori     r6,r6,0xFFFC        /* to start at addr 0x00000004) */
    addis   r9,r0,0x0000        /* set r9 to test value */
                                /* r4 contains the end address */
    rlwinm  r4,r4,29,0xFFFFFFFF /* r4 contains the end address */
                                /* divide by 8 to get loop count */
    mtctr   r4
    mr  r10,r4  /* set r10 to end address (used below) */
    /*
     * At this point the data cache should be enabled to ensure 64 bit 
     * writes done for ECC memory init. It was enabled previously.
     */
..loopz:
    stwu    r9,0x8(r3)  /* store test value */
    stwu    r9,0x8(r6)  /* store test value */
    bdnz    ..loopz

    sync                /* ensure stores complete before  */
                        /* enabling ECC correction */

    /*
     * With memory now initialized and ECC enabled, enable ECC
     * correction. Enable in bank 0 and check # of banks in r5 
     * to determine if bank 1 should be enabled as well.
     * ECC correction is enabled on a per bank basis via the ECCCF reg 
     * bits 8:15.
     */
    addis   r9,0,0x0080     /* set bank 0 correction bit */
    cmpi    0,0,r5,0x2      /* check # of 64-bit banks in r5 */
    bne     ..set_ecccf             
    oris    r9,r9,0x0040    /* set bank 1 correction bit */
..set_ecccf:
    /*
     * Set ECCCF reg to enable correction.
     */
    addi    r2,0,mem_ecccf
    mtdcr   memcfga,r2
    mtdcr   memcfgd,r9
    sync

    /*
     * May call ..whups if we fail. ..whups expects failing addr in r3,
     * expected value in r4, and actual value in r7. Since we need the
     * value in r4 for the end addr, move it to r10 before setting r4
     * to the expected value.
     */
    mr  r10,r4                      /* set r10 to end address (used below) */
    addis   r3,r0,0xFFFF            /* set r3 to start address (used */
    ori     r3,r3,0xFFFC            /* to start at addr 0x00000000) */
    addis   r4,0,0x0                /* set r4 to value expected  */
    rlwinm  r10,r10,30,0xFFFFFFFF   /* r10 contains the end address */
                                    /* divide by 4 to get loop count */
    mtctr   r10
..chk0loop:
    lwzu    r7,0x4(r3)              /* load test value */
    cmpl    cr0,r7,r4               /* compare read value to written value */
    bne     ..whups                 /* branch to error if not the same */
    bdnz    ..chk0loop             

..ecc_disabled:

#endif

    mtlr    r31                     /* restore lr */
    blr

..whups:
    /* Move to non volatiles. */
    addi    r14,r3,0x0              /* failing address */
    addi    r15,r4,0x0              /* set value */
    addi    r16,r7,0x0              /* actual value */
    /*
     * Format and print out failing addresss here......
     */
    addis   r3,r0,..dfail_string@h
    ori     r3,r3,..dfail_string@l
    bl      put_string
    addis   r3,r0,..fail_addr@h
    ori     r3,r3,..fail_addr@l
    bl      put_string
    addi    r3,r14,0x0              /* get failing address */
    bl      prt_word
    addis   r3,r0,..newline@h
    ori     r3,r3,..newline@l
    bl      put_string
    addis   r3,r0,..fail_testval@h
    ori     r3,r3,..fail_testval@l
    bl      put_string
    addi    r3,r15,0                /* get set value */
    bl      prt_word
    addis   r3,r0,..newline@h
    ori     r3,r3,..newline@l
    bl      put_string
    addis   r3,r0,..fail_actual@h
    ori     r3,r3,..fail_actual@l
    bl      put_string
    addi    r3,r16,0x0              /* get actual */
    bl      prt_word
    addis   r3,r0,..newline@h
    ori     r3,r3,..newline@l