reset.s

完整的Bell实验室的嵌入式文件系统TFS

    .globl  invalidate_dcache    

invalidate_dcache:    
    addi    r5,0,0x0000     /* clear GPR 6 */
    addi    r7,r0, 128      /* do loop for # of dcache lines */
                            /* NOTE: dccci invalidates both  */
    mtctr   r7              /* ways in the D cache */
..dcloop:
    dccci   0,r5            /* invalidate line */
    addi    r5,r5, 32       /* bump to next line */
    bdnz    ..dcloop
    blr

/****************************************************************************
 *
 * Function:     ext_busctl_init
 * Description:  Initializes the External Bus Controller for the external 
 *      peripherals. IMPORTANT: This code must run from cache
 *      since you can not reliably change a peripheral banks
 *      timing register (pbxap) while running code from that bank.
 *      For ex., since we are running from ROM on bank 0, we can NOT 
 *      execute the code that modifies bank 0 timings from ROM, so
 *      we run it from cache.
 *  Bank 0 - Flash/SRAM 
 *  Bank 1 - NVRAM/RTC
 *  Bank 2 - KYBD/Mouse Controller
 *  Bank 3 - IRDA
 *  Bank 4 - Pinned out to Expansion connector
 *  Bank 5 - Pinned out to Expansion connector
 *  Bank 6 - Pinned out to Expansion connector
 *  Bank 7 - FPGA regs 
 */
    .text
    .align 2
    .globl  ext_busctl_init

ext_busctl_init:

    addis   r4,r0, I_CACHEABLE_REGIONS@h
    ori     r4,r4, I_CACHEABLE_REGIONS@l

    mficcr  r9                      /* get iccr value */
    cmp     cr0,0,r9,r4             /* check if caching already enabled */
    beq     ..icache_on             /* if not, */
    mticcr  r4                      /* enable caching  */
..icache_on:
    addis   r3,0,ext_busctl_init@h  /* store the address of the  */
    ori     r3,r3,ext_busctl_init@l /* ext_busctl_init functn in r3 */
    addi    r4,0,11                 /* set ctr to 10; used to prefetch */
    mtctr   r4                      /* 10 cache lines to fit this function */
                                    /* in cache (gives us 8x10=80 instrctns) */
..ebcloop:
    icbt    r0,r3                   /* prefetch cache line for addr in r3 */
    addi    r3,r3,32                /* move to next cache line */
    bdnz    ..ebcloop               /* continue for 10 cache lines */

/* Delay to ensure all accesses to ROM are complete before changing
 * bank 0 timings. 200usec should be enough.
 *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
 */
    addis   r3,0,0x0
    ori     r3,r3,0xA000            /* ensure 200usec have passed since reset */
    mtctr   r3
..spinlp:
    bdnz    ..spinlp                /* spin loop */

/* Memory Bank 0 (Flash/SRAM) initialization */
    addi    r4,0,pb0ap
    mtdcr   ebccfga,r4
    addis   r4,0,0x9B01
    ori     r4,r4,0x5480
    mtdcr   ebccfgd,r4

    addi    r4,0,pb0cr
    mtdcr   ebccfga,r4
    addis   r4,0,0xFFF1             /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
    ori     r4,r4,0x8000            /* BW=0x0(8 bits) */
    mtdcr   ebccfgd,r4

/*
 * Memory Bank 1 (NVRAM/RTC) initialization
 */
    addi    r4,0,pb1ap
    mtdcr   ebccfga,r4
    addis   r4,0,0x0281         
    ori     r4,r4,0x5480
    mtdcr   ebccfgd,r4

    addi    r4,0,pb1cr
    mtdcr   ebccfga,r4
    addis   r4,0,0xF001             /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
    ori     r4,r4,0x8000            /* BW=0x0(8 bits) */
    mtdcr   ebccfgd,r4

/*
 * Memory Bank 2 (KYBD/Mouse) initialization
 */
    addi    r4,0,pb2ap
    mtdcr   ebccfga,r4
    addis   r4,0,0x0481
    ori     r4,r4,0x5A80
    mtdcr   ebccfgd,r4

    addi    r4,0,pb2cr
    mtdcr   ebccfga,r4
    addis   r4,0,0xF011             /* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W), */
    ori     r4,r4,0x8000            /* BW=0x0(8 bits) */
    mtdcr   ebccfgd,r4

/*
 * Memory Bank 3 (IRDA) initialization
 */
    addi    r4,0,pb3ap
    mtdcr   ebccfga,r4
    addis   r4,0,0x0181         
    ori     r4,r4,0x5280
    mtdcr   ebccfgd,r4

    addi    r4,0,pb3cr
    mtdcr   ebccfga,r4
    addis   r4,0,0xF021             /* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W), */
    ori     r4,r4,0x8000            /* BW=0x0(8 bits) */
    mtdcr   ebccfgd,r4

/*
 * Memory Bank 7 (FPGA regs) initialization
 */
    addi    r4,0,pb7ap
    mtdcr   ebccfga,r4
#ifdef PASS2_405GP
    addis   r4,0,0x0181             /* TWT=3 (RevB/c errate #24) */        
#else
    addis   r4,0,0x0101             /* TWT=2 */
#endif
    ori     r4,r4,0x5280
    mtdcr   ebccfgd,r4

    addi    r4,0,pb7cr
    mtdcr   ebccfga,r4
    addis   r4,0,0xF031             /* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W), */
    ori     r4,r4,0x8000            /* BW=0x0(8 bits) */
    mtdcr   ebccfgd,r4

    cmpi    cr0,0,r9,0x0            /* check if I cache was off when we */
    /* started 
    bne     ..ebc_done              /* if it was on, leave on */
    addis   r4,r0,0x0000            /* if it was off, disable */
    mticcr  r4                      /* restore iccr */
    isync

..ebc_done:
    blr


/****************************************************************************
 *
 * Function:     ppcDflush
 * Description:  Flush the data cache. This function does NOT turn off the data
 *               cache after the flush. This function makes use of memory
 *               that hopefully should never be in the data cache under normal
 *               circumstances.
 *                       0xFFFFE000-0xFFFFFFFF
 * Input:        none
 * Output:       none
 */
    .text
    .align  2
    .globl  ppcDflush

ppcDflush:
    addis   r9,r0,0x0002        /* set mask for EE and CE msr bits */
    ori     r9,r9,0x8000
    mfmsr   r12                 /* save msr */
    andc    r9,r12,r9
    mtmsr   r9                  /* disable EE and CE */
    addi    r10,r0,0x0001       /* enable data cache for unused memory */
    mfdccr  r9                  /* region 0xF8000000-0xFFFFFFFF via */
    or      r10,r10,r9          /* bit 31 in dccr */
    mtdccr  r10
    addi    r10,r0,128          /* do loop for # of lines */
    addi    r11,r0,4096         /* D cache set size=4K */
    mtctr   r10
    ori     r10,r0,0xE000       /* start at 0xFFFFE000 */
    add     r11,r10,r11         /* add to get to other side of cache line */
..ppcDflush_loop:
    lwz     r3,0(r10)           /* least recently used side */
    lwz     r3,0(r11)           /* the other side */
    dccci   r0,r11              /* invalidate both sides */
    addi    r10,r10,0x0020      /* bump to next line (32 bytes) */
    addi    r11,r11,0x0020      /* bump to next line (32 bytes) */
    bdnz    ..ppcDflush_loop
    sync                        /* allow memory access to complete */
    mtdccr  r9                  /* restore dccr */
    mtmsr   r12                 /* restore msr */
    blr

/****************************************************************************
 *
 * Subroutine: calc_speed
 * Returns the period of the 405GP SYS_CLOCK in nanoseconds. This value can 
 * then be used to calculate the CPU, PLB, OPB, PCI, and timer speeds. 
 * Here we read FPGA_REG_6 to determine whether the on-board clock or an
 * external clock is being used. If the on-board clock is being used, the 
 * 405GP SYS_CLOCK is 33.33Mhz and thus its period is 30ns.
 * If an external clock is being used, then a 41.66Mhz clock is ASSUMED.
 * A 41.66Mhz clock corresponds to a period of 24ns. Of course if 
 * the actual external clock is any thing else but 41.66Mhz, this would be a
 * bad assumption. 
 */
    .text
    .align  2
    .global calc_speed

calc_speed:
    addis   r5,r0,FPGA_BRDS2@h  /* set offset for FPGA_REG_6 */
    ori     r5,r5,FPGA_BRDS2@l
    lbz     r5,0x0(r5)          /* read to get 405GP clk info */
    andi.   r4,r5,0x20          /* check if ext clock selected */
    beq     ..freq33            /* if not set, then 33.33Mhz (30ns) */
    addi    r3,r0,24            /* else ASSUME ext clk is 41.66Mhz   */
                                /* which is a 24ns period.  */
    b       ..end
..freq33:
    addi    r3,r0,30            /* 33.33Mhz => 30ns period  */
..end:
    blr


/****************************************************************************
 *
 * Function:     sdram_init
 * Description:  Configures SDRAM memory banks.
 *      Auto Memory Configuration option reads the SDRAM EEPROM 
 *      via the IIC bus and then configures the SDRAM memory
 *      banks appropriately. If Auto Memory Configuration is
 *      is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
 *      plugged, ie. the DIMM that shipped wih the Eval board.
 */
    .text
    .align 2
    .globl  sdram_init

sdram_init:
    mflr    r31

#ifndef AUTO_MEMORY_CONFIG
    /*
     * Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(2)
     */
    addi    r4,0,mem_mb0cf
    mtdcr   memcfga,r4
    addis   r4,0,0x0004
    ori     r4,r4,6001
    mtdcr   memcfgd,r4

#ifdef SECOND_BANK
    /*
     * Set MB2CF for bank 2. (16MB-32MB) Address Mode 4 since 12x8(2)
     */
    addi    r4,0,mem_mb2cf
    mtdcr   memcfga,r4
    addis   r4,0,0x0104
    ori     r4,r4,6001
    mtdcr   memcfgd,r4
#endif
    /*
     * Take defaults for SDRAM Timing reg, SDTR1.
     */

    /*
     * Delay to ensure 200usec have elapsed since reset. Assume worst
     * case that the core is running 200Mhz:
     *   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
     */
    addis   r3,0,0x0000
    ori     r3,r3,0xA000        /* ensure 200usec have passed since reset */
    mtctr   r3
..spinlp2:
    bdnz    ..spinlp2           /* spin loop */

    /*
     * Set memory controller options reg, MCOPT1.
     * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst 
     * read/prefetch.
     */
    addi    r4,0,mem_mcopt1
    mtdcr   memcfga,r4
    addis   r4,0,0x8080         /* set DC_EN=1 */
    ori     r4,r4,0000
    mtdcr   memcfgd,r4

    /*
     * Delay to ensure 10msec have elapsed since reset. This is
     * required for the MPC952 to stabalize. Assume worst
     * case that the core is running 200Mhz:
     *   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
     * This delay should occur before accessing SDRAM.
     */
    addis   r3,0,0x001E
    ori     r3,r3,0x8480        /* ensure 10msec have passed since reset */
    mtctr   r3
..spinlp3:
    bdnz    ..spinlp3           /* spin loop */



#else     

/*
 * Memory Auto configuration. Reads EEPROM on the SDRAM DIMM via IIC and sets
 * the SDRAM controller appropriately. Handles ECC as well. 
 */
    /*
     * Read bytes of interest on SDRAM EEPROM via iic_read subroutine.
     * These values are required to configure the SDRAM controller
     * properly. Data is stored in regs 4, 5, 6, and 7.
     */
    addi    r4,0,0x00
    addi    r5,0,0x00
    addi    r3,0,3              /* set byte to read (# ROWS) */
    bl      iic0_read
    ori     r4,r3,0x00          /* store value in R4 */
    addi    r3,0,4              /* set byte to read (# COLS) */
    bl      iic0_read
    rlwinm  r4,r4,8,0xFFFFFFFF  /* make room for byte */
    or      r4,r3,r4            /* store value in R4 */
    addi    r3,0,17             /* set byte to read (# INT BANKS) */
    bl      iic0_read
    rlwinm  r4,r4,8,0xFFFFFFFF  /* make room for byte */
    or      r4,r3,r4            /* store value in R4 */
    addi    r3,0,5              /* set byte to read (# BANKS) */
    bl      iic0_read
    ori     r5,r3,0x00          /* store value in R5 */
    addi    r3,0,6              /* set byte to read (DATA WIDTH) */
    bl      iic0_read
    ori     r6,r3,0x00          /* store value in R6 */
    addi    r3,0,31             /* set byte to read (BANK SIZE) */
    bl      iic0_read
    ori     r7,r3,0x00          /* store value in R7 */

    /* ELS Note:
     * With the eval board we got from IBM, the content of R4-R7
     * are as follows at this point...
     * R4: 0x000c0804, R5: 0x00000001, R6: 0x00000048, R7: 0x00000008
     */
    /*
     * Now we have all the data from the SDRAM EEPROM needed in regs 4, 5
     * 6 and 7. Reg 4 has # rows, # cols, and # internal banks in 3 LSBytes.
     * Reg 5 has # banks, Reg 6 has data width, and Reg 7 bank size. No more
     * iic reads are needed. Now the memory controller needs to be set
     * up properly based on the data from the SDRAM EEPROM.
     */

    /*
     * Check r4 values to determine mode. Mode is determined by the
     * # rows, # cols, and # of internal banks. All three of these
     * parameters are stored in r4. Mode should be set as follows:
     *               rows x cols (internal banks)
     *   mode 1 - 11x9(2), 11X10(2)
     *   mode 2 - 12x9(4), 12x10(4)
     *   mode 3 - 13x9(4), 13x10(4), 13x11(4)
     *   mode 4 - 12x8(2), 12x8(4)
     *   mode 5 - 11x8(2), 11x8(4)
     *   mode 6 - 13x8(2), 13x8(4)
     *   mode 7 - 13x9(2), 13x10(2)           
     * The mode must be programmed in each of the Memory Configuration
     * regs (MBxCF) for each enabled bank of SDRAM. Since we only have
     * one DIMM on the Walnut board, the mode will be the same for
     * each enabled SDRAM bank.
     */
    addis   r14,0,0x0B
    ori     r14,r14,0x0902
    cmp     0,0,r4,r14          /* 11x9(2) */
    beq     ..mode1
    addis   r14,0,0x0B
    ori     r14,r14,0x0A02
    cmp     0,0,r4,r14          /* 11x10(2) */
    beq     ..mode1
    addis   r14,0,0x0C
    ori     r14,r14,0x0904
    cmp     0,0,r4,r14          /* 12x9(4) */
    beq     ..mode2
    addis   r14,0,0x0C
    ori     r14,r14,0x0A04
    cmp     0,0,r4,r14          /* 12x10(4) */
    beq     ..mode2
    addis   r14,0,0x0D
    ori     r14,r14,0x0904
    cmp     0,0,r4,r14          /* 13x9(4) */
    beq     ..mode3
    addis   r14,0,0x0D