📄 asm_ppc.s
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*/ .text .align 2 .globl ppcMfdccrppcMfdccr: mfspr r3,dccr blr/* * Function: ppcOrMsr * Description: OR With Machine State Register (MSR) * Input: r3 = value to OR with MSR * Output: r3 = old MSR contents */ .text .align 2 .globl ppcOrMsrppcOrMsr: mfmsr r6 or r7,r6,r3 mtmsr r7 ori r3,r6,0x0000 blr/* * Function: ppcSync * Description: Processor Synchronize * Input: none. * Output: none. */ .text .align 2 .globl ppcSyncppcSync: sync blr/* * Function: ppcEieio * Description: Enforce in-order execution of I/O * Input: none. * Output: none. */ .text .align 2 .globl ppcEieioppcEieio: eieio blr/* * On-chip-memory (ocm) register access functions * for the PPC405: */ .text .align 2 .globl ppcMtocm0isarcppcMtocm0isarc: mtdcr ocm0_isarc,r3 blr .text .align 2 .globl ppcMtocm0isctlppcMtocm0isctl: mtdcr ocm0_isctl,r3 blr .text .align 2 .globl ppcMtocm0dsarcppcMtocm0dsarc: mtdcr ocm0_dsarc,r3 blr .text .align 2 .globl ppcMtocm0dsctlppcMtocm0dsctl: mtdcr ocm0_dsctl,r3 blr .text .align 2 .globl ppcMfocm0isarcppcMfocm0isarc: mfdcr r3,ocm0_isarc blr .text .align 2 .globl ppcMfocm0isctlppcMfocm0isctl: mfdcr r3,ocm0_isctl blr .text .align 2 .globl ppcMfocm0dsarcppcMfocm0dsarc: mfdcr r3,ocm0_dsarc blr .text .align 2 .globl ppcMfocm0dsctlppcMfocm0dsctl: mfdcr r3,ocm0_dsctl blr .text .align 2 .globl ppcMfcntrl0ppcMfcntrl0: mfdcr r3,cntrl0 blr .text .align 2 .globl ppcMtcntrl0ppcMtcntrl0: mtdcr cntrl0,r3 blr .text .align 2 .globl ppcMfcpc0erppcMfcpc0er: mfdcr r3,cpc0_er blr .text .align 2 .globl ppcMtcpc0erppcMtcpc0er: mtdcr cpc0_er,r3 blr .text .align 2 .globl ppcMtspppcMtsp: mr r1,r3 blr .text .align 2 .globl ppcMfspppcMfsp: mr r3,r1 blr .text .align 2 .globl ppcMfcrppcMfcr: mfcr r3 blr .text .align 2 .globl ppcMtcrppcMtcr: mtcr r3 blr/* * Debug (PPC403/405) register access: */ .text .align 2 .globl ppcMtdbcr0ppcMtdbcr0: mtspr dbcr0,r3 blr .text .align 2 .globl ppcMfdbcr0ppcMfdbcr0: mfspr r3,dbcr0 blr .text .align 2 .globl ppcMtdbcr1ppcMtdbcr1: mtspr dbcr1,r3 blr .text .align 2 .globl ppcMfdbcr1ppcMfdbcr1: mfspr r3,dbcr1 blr .text .align 2 .globl ppcMtdbsrppcMtdbsr: mtspr dbsr,r3 blr .text .align 2 .globl ppcMfdbsrppcMfdbsr: mfspr r3,dbsr blr .text .align 2 .globl ppcMtiac1ppcMtiac1: mtspr iac1,r3 blr .text .align 2 .globl ppcMfiac1ppcMfiac1: mfspr r3,iac1 blr .text .align 2 .globl ppcMtiac2ppcMtiac2: mtspr iac2,r3 blr .text .align 2 .globl ppcMfiac2ppcMfiac2: mfspr r3,iac2 blr .text .align 2 .globl ppcMtiac3ppcMtiac3: mtspr iac3,r3 blr .text .align 2 .globl ppcMfiac3ppcMfiac3: mfspr r3,iac3 blr .text .align 2 .globl ppcMtiac4ppcMtiac4: mtspr iac4,r3 blr .text .align 2 .globl ppcMfiac4ppcMfiac4: mfspr r3,iac4 blr .text .align 2 .globl ppcMtdac1ppcMtdac1: mtspr dac1,r3 blr .text .align 2 .globl ppcMfdac1ppcMfdac1: mfspr r3,dac1 blr .text .align 2 .globl ppcMtdac2ppcMtdac2: mtspr dac2,r3 blr .text .align 2 .globl ppcMfdac2ppcMfdac2: mfspr r3,dac2 blr .text .align 2 .globl ppcMtdvc1ppcMtdvc1: mtspr dvc1,r3 blr .text .align 2 .globl ppcMfdvc1ppcMfdvc1: mfspr r3,dvc1 blr .text .align 2 .globl ppcMtdvc2ppcMtdvc2: mtspr dvc2,r3 blr .text .align 2 .globl ppcMfdvc2ppcMfdvc2: mfspr r3,dvc2 blr .text .align 2 .globl ppcMtexierppcMtexier: mtdcr exier,r3 blr .text .align 2 .globl ppcMfexierppcMfexier: mfdcr r3,exier blr .text .align 2 .globl ppcMtexisrppcMtexisr: mtdcr exisr,r3 blr .text .align 2 .globl ppcMfexisrppcMfexisr: mfdcr r3,exisr blr .text .align 2 .globl ppcMtimmrppcMtimmr: mtspr immr,r3 blr .text .align 2 .globl ppcMfimmrppcMfimmr: mfspr r3,immr blr .text .align 2 .globl ppcMtdabrppcMtdabr: mtspr 1013,r3 blr .text .align 2 .globl ppcMtiabrppcMtiabr: mtspr 1010,r3 blr/* * void ppc_flushDcache(char *addr, unsigned int size) * * Assumes R3=addr, R4=size. * Flush d-cache for size bytes starting at addr. */ .global ppc_flushDcacheppc_flushDcache: add r4,r3,r4 /* Last address to flush */ clrrwi r3,r3,4 /* Clear low 4 bits */flush_loop: dcbf r0,r3 /* Flush data block pointed to by r3 */ addi r3,r3,16 /* Advance to next block */ cmplw r3,r4 ble flush_loop sync blr /* * void ppc_invalidateIcache(char *addr, unsigned int size) * * Assumes r3=addr, r4=size and r5=scratch. * Invalidate i-cache for size bytes starting at addr. * */ .global ppc_invalidateIcacheppc_invalidateIcache: add r4,r3,r4 /* Last address to flush */ clrrwi r3,r3,4 /* Clear low 4 bits */inv_loop: icbi r0,r3 /* Invalidate instr block pointed to by r3 */ addi r3,r3,16 /* Advance to next block */ cmplw r3,r4 ble inv_loop isync blr .global rlwtry .global rlwtry1 /* This assembler instruction confuses me everytime I have to * understand how it works, so I figured it would be worth it * to have these two examples to refer to... * * rlwinm RA,RS,SH,MB,ME * * Shift RS left 'SH' bits; then AND that with the mask established * by MB & ME and put the result into RA. * * Look at the examples below... * * The shift value is 0, with MB,ME set to 3,5 * Recall that bit numbers start from the left for PPC... * Literally... * Starting at bit position MB (inclusive) and moving right, all bits * from MB to ME are set to create the mask. If MB is greater than ME, * then when we get to 31, just wrap around to bit zero and continue. * */rlwtry: xor r3,r3,r3 addis r3,r0,0xffff ori r3,r3,0xffff rlwinm r3,r3,0,3,5 /* Mask = 0x1c000000 */ blrrlwtry1: xor r3,r3,r3 addis r3,r0,0xffff ori r3,r3,0xffff rlwinm r3,r3,0,5,3 /* Mask = 0xf7ffffff */ blr⌨️ 快捷键说明
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