arch_ppc.h

完整的Bell实验室的嵌入式文件系统TFS

#define dbat1u  538
#define dbat1l  539
#define dbat2u  540
#define dbat2l  541
#define dbat3u  542
#define dbat3l  543
#define pvr     287
#define l2cr    1017

/* general BAT defines for bit settings to compose BAT regs */
/* represent all the different block lengths */
/* The BL field is part of the Upper Bat Register */
#define BAT_BL_128K     0x00000000
#define BAT_BL_256K     0x00000004
#define BAT_BL_512K     0x0000000C
#define BAT_BL_1M       0x0000001C
#define BAT_BL_2M       0x0000003C
#define BAT_BL_4M       0x0000007C
#define BAT_BL_8M       0x000000FC
#define BAT_BL_16M      0x000001FC
#define BAT_BL_32M      0x000003FC
#define BAT_BL_64M      0x000007FC
#define BAT_BL_128M     0x00000FFC
#define BAT_BL_256M     0x00001FFC

/* supervisor/user valid mode definitions - Upper BAT*/
#define BAT_VALID_SUPERVISOR    0x00000002
#define BAT_VALID_USER          0x00000001
#define BAT_INVALID             0x00000000

/* WIMG bit settings - Lower BAT */
#define BAT_WRITE_THROUGH       0x00000040
#define BAT_CACHE_INHIBITED     0x00000020
#define BAT_COHERENT            0x00000010
#define BAT_GUARDED             0x00000008

/* Protection bits - Lower BAT */
#define BAT_NO_ACCESS           0x00000000
#define BAT_READ_ONLY           0x00000001
#define BAT_READ_WRITE          0x00000002

/* Bit defines for the L2CR register */
#define L2CR_L2E                0x80000000  /* bit 0 - enable */
#define L2CR_L2PE               0x40000000  /* bit 1 - data parity */
#define L2CR_L2SIZ_2M           0x00000000  /* bits 2-3 2 MB; MPC7400 ONLY! */
#define L2CR_L2SIZ_1M           0x30000000  /* bits 2-3 1MB */
#define L2CR_L2SIZ_HM           0x20000000  /* bits 2-3 512K */
#define L2CR_L2SIZ_QM           0x10000000  /* bits 2-3 256K; MPC750 ONLY */
#define L2CR_L2CLK_1            0x02000000  /* bits 4-6 Clock Ratio div 1 */
#define L2CR_L2CLK_1_5          0x04000000  /* bits 4-6 Clock Ratio div 1.5 */
#define L2CR_L2CLK_2            0x08000000  /* bits 4-6 Clock Ratio div 2 */
#define L2CR_L2CLK_2_5          0x0a000000  /* bits 4-6 Clock Ratio div 2.5 */
#define L2CR_L2CLK_3            0x0c000000  /* bits 4-6 Clock Ratio div 3 */
#define L2CR_L2RAM_BURST        0x01000000  /* bits 7-8 burst SRAM */
#define L2CR_DO                 0x00400000  /* bit 9 Enable caching of instr */
                                            /* in L2 */
#define L2CR_L2I                0x00200000  /* bit 10 Global invalidate bit */
#define L2CR_TS                 0x00040000  /* bit 13 Test support on */
#define L2CR_TS_OFF             ~L2CR_TS    /* bit 13 Test support off */
#define L2CR_L2OH_5             0x00000000  /* bits 14-15 Output Hold */
                                            /* time = 0.5ns */
#define L2CR_L2OH_1             0x00010000  /* bits 14-15 Output Hold */
                                            /* time = 1.0ns */
#define L2CR_L2OH_INV           0x00020000  /* bits 14-15 Output Hold */
                                            /* time = 1.0ns */

/* PPC405GP-specific DCRs ...
 */
#define ocm0_isarc  0x018   /* OCM instruction side address range compare   */
#define ocm0_isctl  0x019   /* OCM instruction side control                 */
#define ocm0_dsarc  0x01a   /* OCM data side address range compare          */
#define ocm0_dsctl  0x01b   /* OCM data side control                        */
#define cpc0_er   (CNTRL_DCR_BASE+0x9)

/* MPC860 specific... */
/* Most of the 860 masks are provided by the masks860.h file found on  */
/* Motorola's website.  These additional ones are added here so that the */
/* masks860.h file from moto can be left untouched. */
#define EIE         80  /* External Interrupt Enable */
#define EID         81  /* External Interrupt Disable */
#define NRI         82  /* Non Recoverable Interrupt */
#define CMPA        144 /* Comparator A value register */
#define CMPB        145 /* Comparator B value register */
#define CMPC        146 /* Comparator C value register */
#define CMPD        147 /* Comparator D value register */
#define ICR         148 /* Interrupt Cause Register */
#define DER         149 /* Debug Enable Register*/
#define COUNTA      150 /* Breakpoint Counter A value & control reg. */
#define COUNTB      151 /* Breakpoint Counter B value & control reg. */
#define CMPE        152 /* Comparator E value register */
#define CMPF        153 /* Comparator F value register */
#define CMPG        154 /* Comparator G value register */
#define CMPH        155 /* Comparator H value register */
#define LCTRL1      156 /* Load store support comparator Control reg. */
#define LCTRL2      157 /* Load store support AND-OR Control register */
#define ICTRL       158 /* Instruction support Control register */
#define BAR         159 /* Breakpoint Address register */

#define IC_CST      560 /* Instruction Cache Control and Status reg. */
#define IC_ADR      561 /* Instruction Cache Address register */
#define IC_DAT      562 /* Instruction Cache Data port */
#define DC_CST      568 /* Data Cache Control and Status register */
#define DC_ADR      569 /* Data Cache Address register */
#define DC_DAT      570 /* Data Cache Data port*/

#define DPDR        630 /* Development Port Data Register */
#define DPIR        631 /* */
#define IMMR        638 /* */
#define immr        638

#define MI_CTR      784 /* Instruction MMU Control Register */
#define MI_AP       786 /* Instruction MMU Access Protection Register */
#define MI_EPN      787 /* Instruction MMU Effective Number Register */
#define MI_TWC      789 /* Instruction MMU Tablewalk control Register */
#define MI_RPN      790 /* Instruction MMU Real Page Number Port */

#define MD_CTR      792 /* Data MMU Control Register */
#define M_CASID     793 /* CASID register */
#define MD_AP       794 /* Data Access Protection Register */
#define MD_EPN      795 /* Data Effective Number Register */
#define M_TWB       796 /* MMU Tablewalk base register */
#define MD_TWC      797 /* Data Tablewalk control Register */
#define MD_RPN      798 /* Data Real Page Number Port */
#define M_TW        799 /* MMU Tablewalk special register */

#define MI_DBCAM    816 /* Instruction MMU CAM entry read register */
#define MI_DBRAM0   817 /* Instruction MMU RAM entry read register 0 */
#define MI_DBRAM1   818 /* Instruction MMU RAM entry read register 1 */
#define MD_DBCAM    824 /* Data MMU CAM entry read register */
#define MD_DBRAM0   825 /* Data MMU RAM entry read register 0 */
#define MD_DBRAM1   826 /* Data MMU RAM entry read register 1 */

#define PLPRCR_MF7      0x00700000  /* Multiplication factor = 7 */
#define SIUMCR_DBGC3    0x00300000
#define ISCT_SER7       0x00000007  /* Core is not serialized (normal mode) */
                                    /* and no show cycles will be performed */
                                    /* for fetched instructions. */


#define MPTPR_PTP_DIV2  0x2000      /* BRGCLK divided by 2 */
#define MPTPR_PTP_DIV4  0x1000      /* BRGCLK divided by 4 */
#define MPTPR_PTP_DIV8  0x0800      /* BRGCLK divided by 8 */
#define MPTPR_PTP_DIV16 0x0400      /* BRGCLK divided by 16 */
#define MPTPR_PTP_DIV32 0x0200      /* BRGCLK divided by 32 */
#define MPTPR_PTP_DIV64 0x0100      /* BRGCLK divided by 64 */

#define SIUMCR_BASE     0x0000
#define PLPRCR_BASE     0x0284
#define PBPAR_BASE      0x0abc
#define PBDIR_BASE      0x0ab8
#define PBDAT_BASE      0x0ac4
#define SYPCR_BASE      0x0004
#define SWSR_BASE       0x000e
#define CPCR_BASE       0x09c0
#define SIMASK_BASE     0x0014
#define CIPR_BASE       0x0944
#define CIMR_BASE       0x0948
#define SICR_BASE       0x0aec
#define SDCR_BASE       0x0030
#define PISCR_BASE      0x0240
#define MAR_BASE        0x0164
#define MCR_BASE        0x0168
#define MDR_BASE        0x017c
#define MAMR_BASE       0x0170
#define MPTPR_BASE      0x017a
#define BR0_BASE        0x0100
#define OR0_BASE        0x0104
#define BR1_BASE        0x0108
#define OR1_BASE        0x010c
#define BR2_BASE        0x0110
#define OR2_BASE        0x0114

#ifndef ASSEMBLY_ONLY
extern void             ppcAbend(void);
extern unsigned long    ppcAndMsr(unsigned long value);
extern unsigned long    ppcCntlzw(unsigned long value);

extern void             ppcDcbi(void *addr);
extern void             ppcDcbf(void *addr);
extern void             ppcDcbst(void *addr);
extern void             ppcDcbz(void *addr);
extern void             ppcHalt(void);
extern void             ppcIcbi(void *addr);
extern void             ppcIsync(void);
extern unsigned long    ppcMfgpr1(void);
extern unsigned long    ppcMfgpr2(void);
extern unsigned long    ppcMfmsr(void);
extern unsigned long    ppcMfsprg0(void);
extern unsigned long    ppcMfsprg1(void);
extern unsigned long    ppcMfsprg2(void);
extern unsigned long    ppcMfsprg3(void);
extern unsigned long    ppcMfsrr0(void);
extern unsigned long    ppcMfsrr1(void);
extern unsigned long    ppcMfpvr(void);
extern unsigned long    ppcMfdccr(void);
extern unsigned long    ppcMficcr(void);
extern unsigned long    ppcMfevpr(void);
extern void             ppcMtevpr(unsigned long);
extern void             ppcMticcr(unsigned long);
extern void             ppcMtdccr(unsigned long);
extern void             ppcMtmsr(unsigned long msr_value);
extern void             ppcMtsprg0(unsigned long sprg_value);
extern void             ppcMtsprg1(unsigned long sprg_value);
extern void             ppcMtsprg2(unsigned long sprg_value);
extern void             ppcMtsprg3(unsigned long sprg_value);
extern void             ppcMtsrr0(unsigned long srr0_value);
extern void             ppcMtsrr1(unsigned long srr1_value);
extern unsigned long    ppcOrMsr(unsigned long value);
extern void             ppcSync(void);
extern void             ppcEieio(void);

extern void             ppcMtocm0isctl(unsigned long);
extern void             ppcMtocm0isarc(unsigned long);
extern void             ppcMtocm0dsctl(unsigned long);
extern void             ppcMtocm0dsarc(unsigned long);
extern void             ppcMtcntrl0(unsigned long);
extern unsigned long    ppcMfocm0isarc(void);
extern unsigned long    ppcMfocm0isctl(void);
extern unsigned long    ppcMfocm0dsarc(void);
extern unsigned long    ppcMfocm0dsctl(void);
extern unsigned long    ppcMfcntrl0(void);

extern void             ppcMtdbcr0(unsigned long);
extern void             ppcMtdbcr1(unsigned long);
extern void             ppcMtdbsr(unsigned long);
extern void             ppcMtiac1(unsigned long);
extern void             ppcMtiac2(unsigned long);
extern void             ppcMtiac3(unsigned long);
extern void             ppcMtiac4(unsigned long);
extern void             ppcMtdac1(unsigned long);
extern void             ppcMtdac2(unsigned long);
extern void             ppcMtdvc1(unsigned long);
extern void             ppcMtdvc2(unsigned long);
extern void             ppcMtexier(unsigned long);
extern void             ppcMtexisr(unsigned long);
extern void             ppcMtcr(unsigned long);
extern void             ppcMtimmr(unsigned long);
extern void             ppcMtsp(unsigned long);
extern void             ppcMtiabr(unsigned long);
extern void             ppcMtdabr(unsigned long);
extern unsigned long    ppcMfdbcr0(void);
extern unsigned long    ppcMfdbcr1(void);
extern unsigned long    ppcMfdbsr(void);
extern unsigned long    ppcMfiac1(void);
extern unsigned long    ppcMfiac2(void);
extern unsigned long    ppcMfiac3(void);
extern unsigned long    ppcMfiac4(void);
extern unsigned long    ppcMfdac1(void);
extern unsigned long    ppcMfdac2(void);
extern unsigned long    ppcMfdvc1(void);
extern unsigned long    ppcMfdvc2(void);
extern unsigned long    ppcMfsp(void);
extern unsigned long    ppcMfcr(void);
extern unsigned long    ppcMfexier(void);
extern unsigned long    ppcMfexisr(void);
extern unsigned long    ppcMfimmr(void);
#endif