arch_ppc.h

完整的Bell实验室的嵌入式文件系统TFS

#define cr5_0   20
#define cr5_1   21
#define cr5_2   22
#define cr5_3   23

#define cr6_0   24
#define cr6_1   25
#define cr6_2   26
#define cr6_3   27

#define cr7_0   28
#define cr7_1   29
#define cr7_2   30
#define cr7_3   31
/*
 * Special Purpose Registers
 */
#define zpr    0x3b0     /* zone protection register         (403GC) */
#define pid    0x3b1     /* process id register              (403GC) */
#define smr    0x3b8     /* storage mem-coherent (not implemented)   */
#define sgr    0x3b9     /* storage guarded register         (403GC) */
#define dcwr   0x3ba     /* data cache write-thru register   (403GC) */
#define tbhu   0x3cc     /* user-mode time base high         (403GC) */
#define tblu   0x3cd     /* user-mode time base low          (403GC) */
#define icdbdr 0x3d3     /* instruction cache debug data reg (403GC) */
#define esr    0x3d4     /* execption syndrome register              */
#define dear   0x3d5     /* data exeption address register           */
#define evpr   0x3d6     /* exeption vector prefix register          */
#define cdbcr  0x3d7     /* cache debug control register     (403GC) */
#define tsr    0x3d8     /* timer status register                    */
#define tcr    0x3da     /* timer control register                   */
#define pit    0x3db     /* programmable interval timer              */
#define tbhi   0x3dc     /* time base high                           */
#define tblo   0x3dd     /* time base low                            */
#define srr2   0x3de     /* save/restore register 2                  */
#define srr3   0x3df     /* save/restore register 3                  */
#define dbsr   0x3f0     /* debug status register                    */
#define dbcr   0x3f2     /* debug control register                   */
#define dbcr0  0x3f2     /* debug control register 0 (405GP)         */
#define dbcr1  0x3bd     /* debug control register 1 (405GP)         */
#define iac1   0x3f4     /* instruction address comparator 1         */
#define iac2   0x3f5     /* instruction address comparator 2         */
#define iac3   0x3b4     /* instruction address comparator 3 (405GP) */
#define iac4   0x3b5     /* instruction address comparator 4 (405GP) */
#define dac1   0x3f6     /* data address comparator 1                */
#define dac2   0x3f7     /* data address comparator 2                */
#define dvc1   0x3b6     /* data value comparator 1 (405GP)          */
#define dvc2   0x3b7     /* data value comparator 2 (405GP)          */
#define dccr   0x3fa     /* data cache control register              */
#define iccr   0x3fb     /* instruction cache control register       */
#define pbl1   0x3fc     /* protection bound lower 1                 */
#define pbu1   0x3fd     /* protection bound upper 1                 */
#define pbl2   0x3fe     /* protection bound lower 2                 */
#define pbu2   0x3ff     /* protection bound upper 2                 */


/*
 * Device Control Registers
 */
#define exisr       0x40    /* external interrupt status register */
#define exier       0x42    /* external interrupt enable register */
#define br0         0x80    /* bank register 0 */
#define br1         0x81    /* bank register 1 */
#define br2         0x82    /* bank register 2 */
#define br3         0x83    /* bank register 3 */
#define br4         0x84    /* bank register 4 */
#define br5         0x85    /* bank register 5 */
#define br6         0x86    /* bank register 6 */
#define br7         0x87    /* bank register 7 */
#define bear        0x90    /* bus error address register */
#define besr        0x91    /* bus error syndrome register */
#define iocr        0xa0    /* input/output configuration register */
#define dmacr0      0xc0    /* DMA channel control register 0 */
#define dmact0      0xc1    /* DMA count register 0 */
#define dmada0      0xc2    /* DMA destination address register 0 */
#define dmasa0      0xc3    /* DMA source address register 0 */
#define dmacc0      0xc4    /* DMA chained count 0 */
#define dmacr1      0xc8    /* DMA channel control register 1 */
#define dmact1      0xc9    /* DMA count register 1 */
#define dmada1      0xca    /* DMA destination address register 1 */
#define dmasa1      0xcb    /* DMA source address register 1  */
#define dmacc1      0xcc    /* DMA chained count 1 */
#define dmacr2      0xd0    /* DMA channel control register 2 */
#define dmact2      0xd1    /* DMA count register 2 */
#define dmada2      0xd2    /* DMA destination address register 2 */
#define dmasa2      0xd3    /* DMA source address register 2  */
#define dmacc2      0xd4    /* DMA chained count 2 */
#define dmacr3      0xd8    /* DMA channel control register 3  */
#define dmact3      0xd9    /* DMA count register 3 */
#define dmada3      0xda    /* DMA destination address register 3 */
#define dmasa3      0xdb    /* DMA source address register 3  */
#define dmacc3      0xdc    /* DMA chained count 0 */
#define dmasr       0xe0    /* DMA status register */

/*
 * Machine State Register   msr Bit Masks unique to 403GA
 */
#define we  0x40000      /* wait state enable */
#define ce  0x20000      /* critical interrupt enable */
#define MSR_WE  0x40000  /* wait state enable */
#define MSR_CE  0x20000  /* critical interrupt enable */
#define MSR_DE  0x0200   /* debug enable */
#define MSR_PE  0x0008   /* protection enable */
#define MSR_PX  0x0004   /* protection exclusive mode */


#define mtesr   mtspr esr,
#define mtsrr2  mtspr srr2,
#define mtsrr3  mtspr srr3,
#define mtdcwr  mtspr dcwr,
#define mttcr   mtspr tcr,
#define mtevpr  mtspr evpr,
#define mtsgr   mtspr sgr,
#define mtdbsr  mtspr dbsr,
#define mtdccr  mtspr dccr,
#define mticcr  mtspr iccr,

#define mtbr0   mtdcr br0,
#define mtbr1   mtdcr br1,
#define mtbr2   mtdcr br2,
#define mtbr3   mtdcr br3,
#define mtbr4   mtdcr br4,
#define mtbr5   mtdcr br5,
#define mtbr6   mtdcr br6,
#define mtbr7   mtdcr br7,
#define mtbesr  mtdcr besr,
#define mtexier mtdcr exier,
#define mtexisr mtdcr exisr,
#define mtiocr  mtdcr iocr,

/* Note: if building with DIAB compiler, the "\reg", needs to be 
 * changed to "reg".
 */
#ifdef ASSEMBLY_ONLY
    .macro mfexisr  reg
        mfdcr   \reg,exisr
    .endm
    .macro mfexier  reg
        mfdcr   \reg,exier
    .endm
    .macro mfiocr   reg
        mfdcr   \reg,iocr
    .endm
    .macro mfesr    reg
        mfspr   \reg,esr
    .endm
    .macro mfsrr2   reg
        mfspr   \reg,srr2
    .endm
    .macro mfsrr3   reg
        mfspr   \reg,srr3
    .endm
    .macro mftbhu   reg
        mfspr   \reg,tbhu
    .endm
    .macro mftblu   reg
        mfspr   \reg,tblu
    .endm
    .macro mficcr   reg
        mfspr   \reg,iccr
    .endm
    .macro mfdccr   reg
        mfspr   \reg,dccr
    .endm
#endif


/*
 * PPC405GCX Stuff...
 */
#define CNTRL_DCR_BASE  0x0b0
#define SDRAM_DCR_BASE  0x10

#define pb0ap           0x10    /* Peripheral Bank 0 Access Parameters */
#define pb1ap           0x11    /* Peripheral Bank 1 Access Parameters */
#define pb2ap           0x12    /* Peripheral Bank 2 Access Parameters */
#define pb3ap           0x13    /* Peripheral Bank 3 Access Parameters */
#define pb4ap           0x14    /* Peripheral Bank 4 Access Parameters */
#define pb5ap           0x15    /* Peripheral Bank 5 Access Parameters */
#define pb6ap           0x16    /* Peripheral Bank 6 Access Parameters */
#define pb7ap           0x17    /* Peripheral Bank 7 Access Parameters */
#define pb0cr           0x00    /* Peripheral Bank 0 Configuration Register */
#define pb1cr           0x01    /* Peripheral Bank 1 Configuration Register */
#define pb2cr           0x02    /* Peripheral Bank 2 Configuration Register */
#define pb3cr           0x03    /* Peripheral Bank 3 Configuration Register */
#define pb4cr           0x04    /* Peripheral Bank 4 Configuration Register */
#define pb5cr           0x05    /* Peripheral Bank 5 Configuration Register */
#define pb6cr           0x06    /* Peripheral Bank 6 Configuration Register */
#define pb7cr           0x07    /* Peripheral Bank 7 Configuration Register */

#define mem_mcopt1      0x20    /* Memory Controller options 1 */
#define mem_mb0cf       0x40    /* Memory bacnk 0 configuration */
#define mem_mb1cf       0x44    /* Memory bacnk 1 configuration */
#define mem_mb2cf       0x48    /* Memory bacnk 2 configuration */
#define mem_mb3cf       0x4c    /* Memory bacnk 3 configuration */
#define mem_mb4cf       0x50    /* Memory bacnk 4 configuration */
#define mem_mb5cf       0x54    /* Memory bacnk 5 configuration */
#define mem_mb6cf       0x58    /* Memory bacnk 6 configuration */
#define mem_mb7cf       0x5c    /* Memory bacnk 7 configuration */

#define ebccfga         0x12    /* Peripheral Controller Address Register */
#define ebccfgd         0x13    /* Peripheral Controller Address Register */

#define pllmd   (CNTRL_DCR_BASE+0x0)  /* PLL mode  register */
#define cntrl0  (CNTRL_DCR_BASE+0x1)  /* Control 0 register */
#define cntrl1  (CNTRL_DCR_BASE+0x2)  /* Control 1 register */
#define resetr  (CNTRL_DCR_BASE+0x3)  /* reset register */
#define strapr  (CNTRL_DCR_BASE+0x4)  /* strap register */

#define memcfga  (SDRAM_DCR_BASE+0x0)   /* Memory configuration address reg  */
#define memcfgd  (SDRAM_DCR_BASE+0x1)   /* Memory configuration data    reg  */

/* values for memcfga register - indirect addressing of these regs */
#define mem_besra       0x00    /* bus error syndrome reg a */
#define mem_besrsa      0x04    /* bus error syndrome reg set a */
#define mem_besrb       0x08    /* bus error syndrome reg b */
#define mem_besrsb      0x0c    /* bus error syndrome reg set b */
#define mem_bear        0x10    /* bus error address reg */
#define mem_mcopt1      0x20    /* memory controller options 1 */
#define mem_rtr         0x30    /* refresh timer reg */
#define mem_pmit        0x34    /* power management idle timer */
#define mem_mb0cf       0x40    /* memory bank 0 configuration */
#define mem_mb1cf       0x44    /* memory bank 1 configuration */
#define mem_mb2cf       0x48    /* memory bank 2 configuration */
#define mem_mb3cf       0x4c    /* memory bank 3 configuration */
#define mem_sdtr1       0x80    /* timing reg 1 */
#define mem_ecccf       0x94    /* ECC configuration */
#define mem_eccerr      0x98    /* ECC error status */

#define ppcMsrPOW       0x00040000  /* Power Management                */
#define ppcMsrILE       0x00010000  /* Interrupt Little Endian         */
#define ppcMsrEE        0x00008000  /* External Interrupt Enable       */
#define ppcMsrPR        0x00004000  /* Problem State                   */
#define ppcMsrFP        0x00002000  /* Floating-Point Available        */
#define ppcMsrME        0x00001000  /* Machine Check Enable            */
#define ppcMsrFE0       0x00000800  /* Floating-Point Mode 0           */
#define ppcMsrSE        0x00000400  /* Single-Step Trace Enable        */
#define ppcMsrBE        0x00000200  /* Branch Trace Enable             */
#define ppcMsrFE1       0x00000100  /* Floating-Point Mode 1           */
#define ppcMsrIP        0x00000040  /* Interrupt Prefix                */
#define ppcMsrIR        0x00000020  /* Instruction relocate            */
#define ppcMsrDR        0x00000010  /* Data relocate                   */
#define ppcMsrRI        0x00000002  /* Recoverable interrupt           */
#define ppcMsrLE        0x00000001  /* Little Endian                   */

/* PPC750-specific 
 */
#define hid0    1008
#define ibat0u  528
#define ibat0l  529
#define ibat1u  530
#define ibat1l  531
#define ibat2u  532
#define ibat2l  533
#define ibat3u  534
#define ibat3l  535
#define dbat0u  536
#define dbat0l  537