arch_ppc.h

完整的Bell实验室的嵌入式文件系统TFS

/*
 * arch_ppc.h:
 *
 * Some of this is from IBM BSP source code...
 *
 * This source code has been made available to you by IBM on an AS-IS
 * basis.  Anyone receiving this source is licensed under IBM
 * copyrights to use it in any way he or she deems fit, including
 * copying it, modifying it, compiling it, and redistributing it either
 * with or without modifications.  No license under IBM patents or
 * patent applications is to be implied by the copyright license.
 *
 * Any user of this software should understand that IBM cannot provide
 * technical support for this software and will not be responsible for
 * any consequences resulting from the use of this software.
 *
 * Any person who transfers this source code or any derivative work
 * must include the IBM copyright notice, this paragraph, and the
 * preceding two paragraphs in the transferred software.
 *
 * COPYRIGHT   I B M   CORPORATION 1995
 * LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
 *
 *  General notice:
 *  This code is part of a boot-monitor package developed as a generic base
 *  platform for embedded system designs.  As such, it is likely to be
 *  distributed to various projects beyond the control of the original
 *  author.  Please notify the author of any enhancements made or bugs found
 *  so that all may benefit from the changes.  In addition, notification back
 *  to the author will allow the new user to pick up changes that may have
 *  been made by other users after this version of the code was distributed.
 *
 *  Note1: the majority of this code was edited with 4-space tabs.
 *  Note2: as more and more contributions are accepted, the term "author"
 *         is becoming a mis-representation of credit.
 *
 *  Original author:    Ed Sutter
 *  Email:              [e-mail]
 *  Phone:              908-582-2351
 * 
 */

#ifndef MW
 #define    sp   1
 #define    r0   0
 #define    r1   1
 #define    r2   2
 #define    r3   3
 #define    r4   4
 #define    r5   5
 #define    r6   6
 #define    r7   7
 #define    r8   8
 #define    r9   9
 #define    r10   10
 #define    r11   11
 #define    r12   12
 #define    r13   13
 #define    r14   14
 #define    r15   15
 #define    r16   16
 #define    r17   17
 #define    r18   18
 #define    r19   19
 #define    r20   20
 #define    r21   21
 #define    r22   22
 #define    r23   23
 #define    r24   24
 #define    r25   25
 #define    r26   26
 #define    r27   27
 #define    r28   28
 #define    r29   29
 #define    r30   30
 #define    r31   31
#endif

/*
 * Floating Point Registers
 */
 #define    fr0   0
 #define    fr1   1
 #define    fr2   2
 #define    fr3   3
 #define    fr4   4
 #define    fr5   5
 #define    fr6   6
 #define    fr7   7
 #define    fr8   8
 #define    fr9   9
 #define    fr10   10
 #define    fr11   11
 #define    fr12   12
 #define    fr13   13
 #define    fr14   14
 #define    fr15   15
 #define    fr16   16
 #define    fr17   17
 #define    fr18   18
 #define    fr19   19
 #define    fr20   20
 #define    fr21   21
 #define    fr22   22
 #define    fr23   23
 #define    fr24   24
 #define    fr25   25
 #define    fr26   26
 #define    fr27   27
 #define    fr28   28
 #define    fr29   29
 #define    fr30   30
 #define    fr31   31

/*
 * Special Purpose Registers
 */
 #define    xer     0x01        /*  fixed point exception register */
 #define    lr      0x08        /*  link register */
 #define    ctr     0x09        /*  count register */
 #define    srr0    0x1a        /*  save/restore register 0 */
 #define    srr1    0x1b        /*  save/restore register 1 */
 #define    dec     22          /*  decrementer register */
 #define    sprg0   272         /*  special general reg 0 */
 #define    sprg1   273         /*  special general reg 1 */
 #define    sprg2   274         /*  special general reg 2 */
 #define    sprg3   275         /*  special general reg 3 */
 #define    pvr     287         /*  processor version */

/*
 * Machine State Register     msr     Bit Masks
 */
 #define    pow   0x40000        /* Activates power management */
 #define    ile   0x10000        /* Interrupt little Endian */
 #define    ee   0x8000          /* external interrupt*/
 #define    pr   0x4000          /* problem state  */
 #define    fp   0x2000          /* floating point available */
 #define    me   0x1000          /* machine check */
 #define    fe0   0x0800         /* floating  point exception enable */
 #define    se   0x0400          /* single step trace enable*/
 #define    be   0x0200          /* branch trace enable*/
 #define    fe1   0x0100         /* floating  point exception enable*/
 #define    ip   0x0040          /* prefix */
 #define    ir   0x0020          /* instruction relocate*/
 #define    dr   0x0010          /* data relocate*/
 #define    ri   0x0002          /* recoverable exception */
 #define    le   0x0001          /* Little Endian mode */
 #define    MSR_EE   0x8000      /* external interrupt*/
 #define    MSR_PR   0x4000      /* problem state*/
 #define    MSR_FP   0x2000      /* floating point available*/
 #define    MSR_ME   0x1000      /* machine check*/
 #define    MSR_FE0   0x0800     /* floating point exception enable*/
 #define    MSR_SE   0x0400      /* single step trace enable*/
 #define    MSR_FE1   0x0100     /* floating point exception enable*/
 #define    MSR_EP   0x0040      /* prefix*/
 #define    MSR_IR   0x0020      /* instruction relocate*/
 #define    MSR_DR   0x0010      /* data relocate*/
 #define    MSR_RI   0x0002      /* Recoverable interrupt */
 #define    MSR_LE   0x0001      /* Little Endian */


/*
 * Branch Conditions
 */
 #define    false   0x04       /*branch false bo */
 #define    true   0x0c        /*branch true bo*/
 #define    falsectr   0x00    /*dec ctr branch false and ctr != 0 bo*/
 #define    falzezct   0x02    /*dec ctr branch false and ctr  = 0 bo*/
 #define    truectr   0x08     /*dec ctr branch true  and ctr != 0 bo*/
 #define    truezctr   0x0a    /*dec ctr branch true  and ctr  = 0 bo*/
 #define    always   0x14      /*branch unconditional bo*/
 #define    brctr   0x10       /*dec ctr    branch ctr != 0 bo */
 #define    brzctr   0x12      /*dec ctr    branch ctr  = 0 bo */
 #define    lt   0x00          /*less than condition     bit 0   */
 #define    gt   0x01          /*greater than condition     bit 1  */
 #define    eq   0x02          /*equal condition     bit 2 from 0 */
 #define    so   0x03          /*so bit in cr     bit 3  */
 #define    nolk   0x00        /*no link*/
 #define    lk   0x01          /*link*/

/*
 * Branch Conditions Alternate definitions
 */
 #define    BO_dCTR_NZERO_AND_NOT   0
 #define    BO_dCTR_NZERO_AND_NOT_1   1
 #define    BO_dCTR_ZERO_AND_NOT   2
 #define    BO_dCTR_ZERO_AND_NOT_1   3
 #define    BO_IF_NOT   4
 #define    BO_IF_NOT_1   5
 #define    BO_IF_NOT_2   6
 #define    BO_IF_NOT_3   7
 #define    BO_dCTR_NZERO_AND   8
 #define    BO_dCTR_NZERO_AND_1   9
 #define    BO_dCTR_ZERO_AND   10
 #define    BO_dCTR_ZERO_AND_1   11
 #define    BO_IF   12
 #define    BO_IF_1   13
 #define    BO_IF_2   14
 #define    BO_IF_3   15
 #define    BO_dCTR_NZERO   16
 #define    BO_dCTR_NZERO_1   17
 #define    BO_dCTR_ZERO   18
 #define    BO_dCTR_ZERO_1   19
 #define    BO_ALWAYS   20
 #define    BO_ALWAYS_1   21
 #define    BO_ALWAYS_2   22
 #define    BO_ALWAYS_3   23
 #define    BO_dCTR_NZERO_8   24
 #define    BO_dCTR_NZERO_9   25
 #define    BO_dCTR_ZERO_8   26
 #define    BO_dCTR_ZERO_9   27
 #define    BO_ALWAYS_8   28
 #define    BO_ALWAYS_9   29
 #define    BO_ALWAYS_10   30
 #define    BO_ALWAYS_11   31
/*
 * Condition Register Bit Fields
 */
#ifndef MW
 #define    cr0   0
 #define    cr1   1
 #define    cr2   2
 #define    cr3   3
 #define    cr4   4
 #define    cr5   5
 #define    cr6   6
 #define    cr7   7
#endif

/*
 * Condition Register Bit Sub-fields
*/

#define cr0_0   0
#define cr0_1   1
#define cr0_2   2
#define cr0_3   3

#define cr1_0   4
#define cr1_1   5
#define cr1_2   6
#define cr1_3   7

#define cr2_0   8
#define cr2_1   9
#define cr2_2   10
#define cr2_3   11

#define cr3_0   12
#define cr3_1   13
#define cr3_2   14
#define cr3_3   15

#define cr4_0   16
#define cr4_1   17
#define cr4_2   18
#define cr4_3   19