masks860.h

完整的Bell实验室的嵌入式文件系统TFS

#define POR5_PPS    0x00000040    /* PCMCIA Port Size */
#define POR5_PRS    0x00000038    /* PCMCIA Region Select */
#define POR5_PSLOT  0x00000004    /* PCMCIA Slot Identifier */
#define RESERVED24  0x00000002    /* Any write to this window will result
                                      in a bus error */
#define POR5_PV     0x00000001    /* PCMCIA Valid Bit */



/*------------------------------------*
 * Interface Option Register 6 (POR6) *
 *------------------------------------*/

#define POR6_BSIZE  0xF8000000    /* PCMCIA Bank Size */
#define RESERVED25  0x07F00000    
#define POR6_PSHT   0x000F0000    /* PCMCIA Strobe Hold Time */
#define POR6_PSST   0x0000F000    /* PCMCIA Strobe Set Up Time */
#define POR6_PSL    0x00000F80    /* PCMCIA Strobe Length */
#define POR6_PPS    0x00000040    /* PCMCIA Port Size */
#define POR6_PRS    0x00000038    /* PCMCIA Region Select */
#define POR6_PSLOT  0x00000004    /* PCMCIA Slot Identifier */
#define RESERVED26  0x00000002    /* Any write to this window will result
                                      in a bus error */
#define POR6_PV     0x00000001    /* PCMCIA Valid Bit */



/*------------------------------------*
 * Interface Option Register 7 (POR7) *
 *------------------------------------*/

#define POR7_BSIZE  0xF8000000    /* PCMCIA Bank Size */
#define RESERVED27  0x07F00000    
#define POR7_PSHT   0x000F0000    /* PCMCIA Strobe Hold Time */
#define POR7_PSST   0x0000F000    /* PCMCIA Strobe Set Up Time */
#define POR7_PSL    0x00000F80    /* PCMCIA Strobe Length */
#define POR7_PPS    0x00000040    /* PCMCIA Port Size */
#define POR7_PRS    0x00000038    /* PCMCIA Region Select */
#define POR7_PSLOT  0x00000004    /* PCMCIA Slot Identifier */
#define RESERVED28  0x00000002    /* Any write to this window will result
                                      in a bus error */
#define POR7_PV     0x00000001    /* PCMCIA Valid Bit */



/*----------------------------------------------*
 * Interface General Control Register A (PGCRA) *
 *----------------------------------------------*/

#define PGCRA_CAIREQLVL  0xFF000000   /* Define Interrupt Level for 
                                          IREQ for Card A */
#define PGCRA_CASCHLVL   0x00FF0000   /* Define Interupt Level for 
                                          STSCHG for Card A */
#define PGCRA_CADREQ     0x0000C000   /* Define pin to be used as 
                                          internal DMA request */
#define RESERVED29       0x00003F00   
#define PGCRA_CAOE       0x00000080   /* Card A Output Enable */
#define PGCRA_CARESET    0x00000040   /* Card A Reset */

#define RESERVED30       0x0000003F  



/*----------------------------------------------*
 * Interface General Control Register B (PGCRB) *
 *----------------------------------------------*/

#define PGCRB_CBIRQLVL   0xFF000000   /* Define Interrupt Level for 
                                          IREQ for Card B */
#define PGCRB_CBSCHLVL   0x00FF0000   /* Define Interupt Level for 
                                          STSCHG for Card B */
#define PGCRB_CBDREQ     0x0000C000   /* Define pin to be used as 
                                          internal DMA request */
#define RESERVED31       0x00003F00   
#define PGCRB_CBOE       0x00000080   /* Card B Output Enable */
#define PGCRB_CBRESET    0x00000040   /* Card B Reset */

#define RESERVED32       0x0000003F  



/*------------------------------------------*
 * Interface Status Changed Register (PSCR) *
 *------------------------------------------*/

#define PSCR_CAVS1_C     0x80000000   /* Volt. Sense 1 for Card A changed */
#define PSCR_CAVS2_C     0x40000000   /* Volt. Sense 2 for Card A changed */
#define PSCR_CAWP_C      0x20000000   /* Write Protect for Card A changed */
#define PSCR_CACD2_C     0x10000000   /* Card Detect 2 for Card A changed */
#define PSCR_CACD1_C     0x08000000   /* Card Detect 1 for Card A changed */
#define PSCR_CABVD2_C    0x04000000   /* Batt Volt/SPKR in Card A changed */
#define PSCR_CABVD1_C    0x02000000   /* Batt Volt/STSCHG Card A changed */
#define RESERVED33       0x01000000
#define PSCR_CARDY_L     0x00800000   /* RDY/IRQ of Card A Pin is Low */
#define PSCR_CARDY_H     0x00400000   /* RDY/IRQ of CARD A Pin is High */
#define PSCR_CARDY_R     0x00200000   /* RDY/IRQ of Card A Pin Rising Edge 
                                          detected */
#define PSCR_CARDY_F     0x00100000   /* RDY/IRQ of Card A Pin Falling Edge 
                                          detected */
#define RESERVED34       0x000F0000
#define PSCR_CBVS1_C     0x00008000   /* Volt Sense 1 for Card B changed */
#define PSCR_CBVS2_C     0x00004000   /* Volt Sense 2 for Card B changed */
#define PSCR_CBWP_C      0x00002000   /* Write Protect for Card B changed */
#define PSCR_CBCD2_C     0x00001000   /* Card detect 2 for Card B changed */
#define PSCR_CBCD1_C     0x00000800   /* Card detect 1 for Card B changed */
#define PSCR_CBBVD2_C    0x00000400   /* Batt Volt/SPKR in for Card B 
                                          change */
#define PSCR_CBBVD1_C    0x00000200   /* Batt Volt/STSCHG in for Card B 
                                          change */
#define RESERVED35       0x00000100   
#define PSCR_CBRDY_L     0x00000080   /* RDY/IRQ of Card B Pin is Low */
#define PSCR_CBRDY_H     0x00000040   /* RDY/IRQ of Card B Pin is High */
#define PSCR_CBRDY_R     0x00000020   /* RDY/IRQ of Card B Pin Rising 
                                          Edge detect */
#define PSCR_CBRDY_F     0x00000010   /* RDY/IRQ of Card B Pin Falling
                                          Edge detect */
#define RESERVED36       0x0000000F  



/*--------------------------------------*
 * Interface Input Pins Register (PIPR) *
 *--------------------------------------*/

#define PIPR_CAVS1   0x80000000   /* Volt Sense 1 for Card A */
#define PIPR_CAVS2   0x40000000   /* Volt Sense 2 for Card A */
#define PIPR_CAWP    0x20000000   /* Write Protect for Card A */
#define PIPR_CACD2   0x10000000   /* Card Detect 2 for Card A */
#define PIPR_CACD1   0x08000000   /* Card Detect 1 for Card A */
#define PIPR_CABVD2  0x04000000   /* Batt Volt/SPKR in for Card A */
#define PIPR_CABVD1  0x02000000   /* Batt Volt/STSCHG in for Card A */
#define PIPR_CARDY   0x01000000   /* RDY/IRQ of Card A Pin */
#define RESERVED37   0x00FF0000
#define PIPR_CBVS1   0x00008000   /* Voltage Sense 1 for Card B */
#define PIPR_CBVS2   0x00004000   /* Voltage Sense 2 for Card B */
#define PIPR_CBWP    0x00002000   /* Write Protect for Card B */
#define PIPR_CBCD2   0x00001000   /* Card Detect 2 for Card B */
#define PIPR_CBCD1   0x00000800   /* Card Detect 1 for Card B */
#define PIPR_CBBVD2  0x00000400   /* Batt Volt/SPKR in for Card B */
#define PIPR_CBBVD1  0x00000200   /* Batt Volt/STSCHG in for Card B */
#define PIPR_CBRDY   0x00000100   /* RDY/IRQ of Card B Pin */
#define RESERVED38   0x000000FF   
                              


/*---------------------------------*
 * Interface Enable Register (PER) *
 *---------------------------------*/

#define PER_CA_EVS1   0x80000000   /* Enable Volt Sense 1 Card A changed */
#define PER_CA_EVS2   0x40000000   /* Enable Volt Sense 2 Card A changed */
#define PER_CA_EWP    0x20000000   /* Enable Write Prot. Card A Changed */
#define PER_CA_ECD2   0x10000000    /* Enable Card Detect 2 Card A Changed */
#define PER_CA_ECD1   0x08000000   /* Enable Card Detect 2 Card A Changed */
#define PER_CA_EBVD2  0x04000000   /* Enable Batt Volt/SPKR in for Card A
                                       changed */
#define PER_CA_EBVD1  0x02000000   /* Enable for Batt Volt/STSCHG in for 
                                       Card A changed */
#define RESERVED39    0x01000000
#define PER_CA_ERDY_L 0x00800000   /* Enable for RDY/IRQ Card A Pin Low */
#define PER_CA_ERDY_H 0x00400000   /* Enable for RDY/IRQ Card A Pin High */
#define PER_CA_ERDY_R 0x00200000   /* Enable for RDY/IRQ Card A Pin R.E. 
                                       Detected */ 
#define PER_CA_ERDY_F 0x00100000   /* Enable for RDY/IRQ Card A Pin F.E. 
                                       Detected */ 
#define RESERVED40    0x000F0000
#define PER_CB_EVS1   0x00008000   /* Enable Volt Sense 1 Card B Changed */
#define PER_CB_EVS2   0x00004000   /* Enable Volt Sense 2 Card B Changed */
#define PER_CB_EWP    0x00002000   /* Enable for Write Protect for Card B 
                                       Changed */
#define PER_CB_ECD2   0x00001000   /* Enable for Card Detect 2 for Card B 
                                       Changed */
#define PER_CB_ECD1   0x00000800   /* Enable for Card Detect 1 for Card B 
                                       Changed */
#define PER_CB_EBVD2  0x00000400   /* Enable Batt Volt/SPKR in for Card B
                                       Changed */
#define PER_CB_EBVD1  0x00000200   /* Enable for Batt Volt/STSCHG in for 
                                       Card B Changed */
#define RESERVED41    0x00000100   
#define CB_ERDY_L     0x00000080   /* Enable for RDY/IRQ of Card B Pin is 
                                       Low */
#define CB_ERDY_H     0x00000040   /* Enable for RDY/IRQ of Card B Pin is 
                                       High */
#define CB_ERDY_R     0x00000020   /* Enable for RDY/IRQ Card B Pin R.E.
                                       Detected */
#define CB_ERDY_F     0x00000010   /* Enable for RDY/IRQ Card B Pin F.E.
                                       Detected */
#define RESERVED42    0x0000000F  



/*-------------------------------------------------------------------------*
 *                                   MEMC                                  *
 *-------------------------------------------------------------------------*/


/*----------------------------*
 * Base Register Bank 0 (BR0) *
 *----------------------------*/

#define BR0_BA      0xFFFF8000   /* Base Address */
#define BR0_AT      0x00007000   /* Address Type */
#define BR0_PS      0x00000C00   /* Port Size */
#define BR0_PARE    0x00000200   /* Parity Enable */
#define BR0_WP      0x00000100   /* Write protect */
#define BR0_MS      0x000000C0   /* Machine Select */
#define RESERVED43  0x0000003E  
#define BR0_V       0x00000001   /* Valid Bit */ 



/*------------------------------*
 * Option Register Bank 0 (OR0) *
 *------------------------------*/

#define OR0_AM             0xFFFF8000   /* Address Mask */
#define OR0_ATM            0x00007000   /* Address Type Mask */
#define OR0_CSNT_SAM       0x00000800   /* Chip Select Negation Time
                                            Start Address Multiplex */
#define OR0_ACS_G5LA_G5LS  0x00000600   /* Address to Chip-Select Setup 
                                            General-Purpose Line 5A
                                            General-Purpose Line 5 Start */
#define OR0_BI             0x00000100   /* Burst Inhibit */
#define OR0_SCY            0x000000F0   /* cycle Length in Clocks */
#define OR0_SETA           0x00000008   /* External Transfer Acknowledge */
#define OR0_TRLX           0x00000004   /* Timing Relaxed */
#define OR0_EHTR           0x00000002   /* Extended Hold Time Rd. Access */
#define RESERVED44         0x00000001



/*----------------------------*
 * Base Register Bank 1 (BR1) *
 *----------------------------*/

#define BR1_BA      0xFFFF8000   /* Base Address */
#define BR1_AT      0x00007000   /* Address Type */
#define BR1_PS      0x00000C00   /* Port Size */
#define BR1_PARE    0x00000200   /* Parity Enable */
#define BR1_WP      0x00000100   /* Write protect */
#define BR1_MS      0x000000C0   /* Machine Select */
#define RESERVED45  0x0000003E  
#define BR1_V       0x00000001   /* Valid Bit */ 
  


/*------------------------------*
 * Option Register Bank 1 (OR1) *
 *------------------------------*/

#define OR1_AM             0xFFFF8000   /* Address Mask */
#define OR1_ATM            0x00007000   /* Address Type Mask */
#define OR1_CSNT_SAM       0x00000800   /* Chip Select Negation Time
                                           Start Address Multiplex */
#define OR1_ACS_G5LA_G5LS  0x00000600   /* Address to Chip-Select Setup 
                                           General-Purpose Line 5A
                                           General-Purpose Line 5 Start */
#define OR1_BI             0x00000100   /* Burst Inhibit */
#define OR1_SCY            0x000000F0   /* cycle Length in Clocks */
#define OR1_SETA           0x00000008   /* External Transfer Acknowledge */
#define OR1_TRLX           0x00000004   /* Timing Relaxed */
#define OR1_EHTR           0x00000002   /* Extended Hold Time on Read
                                           Access */
#define RESERVED46         0x00000001



/*----------------------------*
 * Base Register Bank 2 (BR2) *
 *----------------------------*/

#define BR2_BA      0xFFFF8000   /* Base Address */
#define BR2_AT      0x00007000   /* Address Type */
#define BR2_PS      0x00000C00   /* Port Size */
#define BR2_PARE    0x00000200   /* Parity Enable */
#define BR2_WP      0x00000100   /* Write protect */
#define BR2_MS      0x000000C0   /* Machine Select */
#define RESERVED47  0x0000003E  
#define BR2_V       0x00000001   /* Valid Bit */ 
  


/*------------------------------*
 * Option Register Bank 2 (OR2) *
 *------------------------------*/

#define OR2_AM             0xFFFF8000   /* Address Mask */
#define OR2_ATM            0x00007000   /* Address Type Mask */
#define OR2_CSNT_SAM       0x00000800   /* Chip Select Negation Time
                                           Start Address Multiplex */
#define OR2_ACS_G5LA_G5LS  0x00000600   /* Address to Chip-Select Setup 
                                           General-Purpose Line 5A
                                           General-Purpose Line 5 Start */
#define OR2_BI             0x00000100   /* Burst Inhibit */
#define OR2_SCY            0x000000F0   /* cycle Length in Clocks */
#define OR2_SETA           0x00000008   /* External Transfer Acknowledge */
#define OR2_TRLX           0x00000004   /* Timing Relaxed */
#define OR2_EHTR           0x00000002   /* Extended Hold Time Rd. Access */
#define RESERVED48         0x00000001



/*----------------------------*
 * Base Register Bank 3 (BR3) *
 *----------------------------*/

#define BR3_BA      0xFFFF8000   /* Base Address */
#define BR3_AT      0x00007000   /* Address Type */
#define BR3_PS      0x00000C00   /* Port Size */
#define BR3_PARE    0x00000200   /* Parity Enable */
#define BR3_WP      0x00000100   /* Write protect */
#define BR3_MS      0x000000C0   /* Machine Select */