📄 mpc860.h
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VUHWORD pio_pcpar; /* port C pin assignment reg */ VUHWORD pio_pcso; /* port C special options */ VUHWORD pio_pcdat; /* port C data register */ VUHWORD pio_pcint; /* port C interrupt cntrl reg */ UBYTE RESERVED49[6]; VUHWORD pio_pddir; /* port D Data Direction reg */ VUHWORD pio_pdpar; /* port D pin assignment reg */ UBYTE RESERVED50[2]; VUHWORD pio_pddat; /* port D data reg */ VUBYTE RESERVED51[0x8]; /* Reserved area */ /*-----------*/ /* CPM Timer */ /*-----------*/ VUHWORD timer_tgcr; /* timer global configuration reg */ VUBYTE RESERVED52[0xe]; /* Reserved area */ VUHWORD timer_tmr1; /* timer 1 mode reg */ VUHWORD timer_tmr2; /* timer 2 mode reg */ VUHWORD timer_trr1; /* timer 1 referance reg */ VUHWORD timer_trr2; /* timer 2 referance reg */ VUHWORD timer_tcr1; /* timer 1 capture reg */ VUHWORD timer_tcr2; /* timer 2 capture reg */ VUHWORD timer_tcn1; /* timer 1 counter reg */ VUHWORD timer_tcn2; /* timer 2 counter reg */ VUHWORD timer_tmr3; /* timer 3 mode reg */ VHWORD timer_tmr4; /* timer 4 mode reg */ VUHWORD timer_trr3; /* timer 3 referance reg */ VUHWORD timer_trr4; /* timer 4 referance reg */ VUHWORD timer_tcr3; /* timer 3 capture reg */ VUHWORD timer_tcr4; /* timer 4 capture reg */ VUHWORD timer_tcn3; /* timer 3 counter reg */ VUHWORD timer_tcn4; /* timer 4 counter reg */ VUHWORD timer_ter1; /* timer 1 event reg */ VUHWORD timer_ter2; /* timer 2 event reg */ VUHWORD timer_ter3; /* timer 3 event reg */ VUHWORD timer_ter4; /* timer 4 event reg */ VUBYTE RESERVED53[0x8]; /* Reserved area */ /*----*/ /* CP */ /*----*/ VUHWORD cp_cr; /* command register */ VUBYTE RESERVED54[0x2]; /* Reserved area */ VUHWORD cp_rccr; /* main configuration reg */ VUBYTE RESERVED55; /* Reserved area */ VUBYTE cp_resv1; /* Reserved reg */ VUWORD cp_resv2; /* Reserved reg */ VUHWORD cp_rctr1; /* ram break register 1 */ VUHWORD cp_rctr2; /* ram break register 2 */ VUHWORD cp_rctr3; /* ram break register 3 */ VUHWORD cp_rctr4; /* ram break register 4 */ VUBYTE RESERVED56[0x2]; /* Reserved area */ VUHWORD cp_rter; /* RISC timers event reg */ VUBYTE RESERVED57[0x2]; /* Reserved area */ VUHWORD cp_rtmr; /* RISC timers mask reg */ VUBYTE RESERVED58[0x14]; /* Reserved area */ /*-----*/ /* BRG */ /*-----*/ VUWORD brgc1; /* BRG1 configuration reg */ VUWORD brgc2; /* BRG2 configuration reg */ VUWORD brgc3; /* BRG3 configuration reg */ VUWORD brgc4; /* BRG4 configuration reg */ /*---------------*/ /* SCC registers */ /*---------------*/ struct scc_regs { VUWORD scc_gsmr_l; /* SCC Gen mode (LOW) */ VUWORD scc_gsmr_h; /* SCC Gen mode (HIGH) */ VUHWORD scc_psmr; /* protocol specific mode register */ VUBYTE RESERVED59[0x2]; /* Reserved area */ VUHWORD scc_todr; /* SCC transmit on demand */ VUHWORD scc_dsr; /* SCC data sync reg */ VUHWORD scc_scce; /* SCC event reg */ VUBYTE RESERVED60[0x2]; /* Reserved area */ VUHWORD scc_sccm; /* SCC mask reg */ VUBYTE RESERVED61[0x1]; /* Reserved area */ VUBYTE scc_sccs; /* SCC status reg */ VUBYTE RESERVED62[0x8]; /* Reserved area */ } scc_regs[4]; /*-----*/ /* SMC */ /*-----*/ struct smc_regs { VUBYTE RESERVED63[0x2]; /* Reserved area */ VUHWORD smc_smcmr; /* SMC mode reg */ VUBYTE RESERVED64[0x2]; /* Reserved area */ VUBYTE smc_smce; /* SMC event reg */ VUBYTE RESERVED65[0x3]; /* Reserved area */ VUBYTE smc_smcm; /* SMC mask reg */ VUBYTE RESERVED66[0x5]; /* Reserved area */ } smc_regs[2]; /*-----*/ /* SPI */ /*-----*/ VUHWORD spi_spmode; /* SPI mode reg */ VUBYTE RESERVED67[0x4]; /* Reserved area */ VUBYTE spi_spie; /* SPI event reg */ VUBYTE RESERVED68[0x3]; /* Reserved area */ VUBYTE spi_spim; /* SPI mask reg */ VUBYTE RESERVED69[0x2]; /* Reserved area */ VUBYTE spi_spcom; /* SPI command reg */ VUBYTE RESERVED70[0x4]; /* Reserved area */ /*-----*/ /* PIP */ /*-----*/ VUHWORD pip_pipc; /* pip configuration reg */ VUBYTE RESERVED71[0x2]; /* Reserved area */ VUHWORD pip_ptpr; /* pip timing parameters reg */ VUWORD pip_pbdir; /* port b data direction reg */ VUWORD pip_pbpar; /* port b pin assignment reg */ VUBYTE RESERVED72[0x2]; /* Reserved area */ VUHWORD pip_pbodr; /* port b open drain reg */ VUWORD pip_pbdat; /* port b data reg */ VUBYTE RESERVED73[0x18]; /* Reserved area */ /*------------------*/ /* Serial Interface */ /*------------------*/ VUWORD si_simode; /* SI mode register */ VUBYTE si_sigmr; /* SI global mode register */ VUBYTE RESERVED74; /* Reserved area */ VUBYTE si_sistr; /* SI status register */ VUBYTE si_sicmr; /* SI command register */ VUBYTE RESERVED75[0x4]; /* Reserved area */ VUWORD si_sicr; /* SI clock routing */ VUWORD si_sirp; /* SI ram pointers */ VUBYTE RESERVED76[0x10c]; /* Reserved area */ VUBYTE si_siram[0x200]; /* SI routing ram */ VUBYTE RESERVED77[0x1200]; /* Reserved area */ /*-----------------------------------------------------------------*/ /* BASE + 0x2000: user data memory, microcode, or QMC channel PRAM */ /*-----------------------------------------------------------------*/ union { struct qmc_chan_pram qcp[64]; struct user_data ud; struct micromon_data umd; UBYTE RESERVED[0x1c00]; } qcp_or_ud; /*-----------------------------------------------------------------------*/ /* BASE + 0x3c00: PARAMETER RAM. This main union defines 4 memory blocks */ /* of an identical size. See the Parameter RAM definition in the MPC860 */ /* user's manual. */ /*-----------------------------------------------------------------------*/ /*------------------------*/ /* Base + 0x3C00 (page 1) */ /* + 0x3D00 (page 2) */ /* + 0x3E00 (page 3) */ /* + 0x3F00 (page 4) */ /*------------------------*/ union { struct page_of_pram { /*------------------------------------------------------------*/ /* scc parameter area - 1st memory block (protocol dependent) */ /*------------------------------------------------------------*/ union { struct hdlc_pram h; struct uart_pram u; struct bisync_pram b; struct transparent_pram t; struct async_hdlc_pram a; UBYTE RESERVED78[0x80]; } scc; /*----------------------------------------------------------------*/ /* Other protocol areas for the rest of the memory blocks in each */ /* page. */ /*----------------------------------------------------------------*/ union { /*---------------------------------------------------------------*/ /* This structure defines the rest of the blocks on the 1st page */ /*---------------------------------------------------------------*/ struct { struct i2c_pram i2c; /* I2C */ struct idma_pram idma1; /* IDMA1 */ } i2c_idma; /*---------------------------------------------------------------*/ /* This structure defines the rest of the blocks on the 2nd page */ /*---------------------------------------------------------------*/ struct { struct spi_pram spi; /* SPI */ struct timer_pram timer; /* Timers */ struct idma_pram idma2; /* IDMA2 */ } spi_timer_idma; /*---------------------------------------------------------------*/ /* This structure defines the rest of the blocks on the 3rd page */ /*---------------------------------------------------------------*/ struct { union { struct smc_uart_pram u1; /* SMC1 */ struct smc_trnsp_pram t1; /* SMC1 */ UBYTE RESERVED78[0x80]; /* declare full block */ } psmc1; } smc_dsp1; /*---------------------------------------------------------------*/ /* This structure defines the rest of the blocks on the 4th page */ /*---------------------------------------------------------------*/ struct { union { struct smc_uart_pram u2; /* SMC2 */ struct smc_trnsp_pram t2; /* SMC2 */ struct centronics_pram c; /* Uses SM2's space */ UBYTE RESERVED79[0x80]; /* declare full block */ } psmc2; } smc_dsp2; UBYTE RESERVED80[0x80]; /* declare full block */ } other; } pg; /*---------------------------------------------------------------*/ /* When selecting Ethernet as protocol for an SCC, this protocol */ /* uses a complete page of Parameter RAM memory. */ /*---------------------------------------------------------------*/ struct ethernet_pram enet_scc; /*---------------------------------------------------------------*/ /* When using QMC as a mode for an SCC, the QMC global parameter */ /* ram uses from SCC BASE to BASE+AC. */ /*---------------------------------------------------------------*/ struct global_qmc_pram gqp; /*--------------------------------------------------------*/ /* declaration to guarantee a page of memory is allocated */ /*--------------------------------------------------------*/ UBYTE RESERVED83[0x100]; } PRAM[4]; /* end of union */} EPPC;/***************************************************************************//* General Global Definitions *//***************************************************************************/#define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */#define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */#define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */#define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */#define SMC1_REG 0 /* SMC1 Index into SMC Regs Array */ #define SMC2_REG 1 /* SMC2 Index into SMC Regs Array */ #define SCC1_REG 0 /* SCC1 Index into SCC Regs Array */ #define SCC2_REG 1 /* SCC2 Index into SCC Regs Array */ #define SCC3_REG 2 /* SCC3 Index into SCC Regs Array */ #define SCC4_REG 3 /* SCC4 Index into SCC Regs Array */ /*--------------------------------*//* KEEP ALIVE POWER REGISTERS KEY *//*--------------------------------*/#define KEEP_ALIVE_KEY 0x55ccaa33⌨️ 快捷键说明
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