mpc860.h

完整的Bell实验室的嵌入式文件系统TFS

/*-----------------------------------------------------------------------------             
*
* File:  MPC860.H
*
* Description:  
*
* Definitions of the parameter area RAM.
* Note that different structures are overlaid
* at the same offsets for the different modes
* of operation.
*
* History:
*
* 12 DEC 95    lvn  Bundled multiple files from MSIL into this file
*
* 18 JUN 96    saw  Replaced:
*
*                   VUWORD  simt_tbscr;
*                    VUWORD simt_rtcsc;
*                    With:
*
*                   VUHWORD simt_tbscr;
*                   VUBYTE  RESERVED100[0x2];
*                   VUHWORD simt_rtcsc;
*                   VUBYTE  RESERVED110[0x2];
*
* 04 OCT 96    saw  Filled in PCMCIA section.
*
* 21 NOV 96    saw  Changed address of PIP PBODR to 0xac2 from 0xac0.
*
* 18 DEC 96    saw  Renamed Registers:
*
*                        scc_gsmra -> scc_gsmr_l
*                        scc_gsmrb -> scc_gsmr_h
*
* 06 JAN 97    sgj  Created 860 version from 8xx code standard
*
* 18 JUL 97    sgj  Corrected mapping of Ucode/BD DPRAM
*
* 08 AUG 97    sgj  Added definitions for key registers for System
*                   Integration timers, Clock, and Reset
*
* 26 AUG 97    sgj  Removed ADS-specific definitions and
*                   reorganized for readability
*
* 20 NOV 97    jay  Added to and cleaned up the parameter map definitions
* 
* 10 FEB 98     jay  Updated IDMA definitions
*
* 18 FEB 98     ggh  Added QMC definitions 
*                   ecg
*
* 01 MAY 98    jay  fixed a parameter ram bug created by the previous 
*                   modifications on 18 FEB 98.
*
*-----------------------------------------------------------------------------*/

#define UHWORD  volatile unsigned short
#define UWORD   volatile unsigned long
#define UBYTE   volatile unsigned char
#define VUBYTE  volatile unsigned char
#define VUHWORD volatile unsigned short
#define VUWORD  volatile unsigned long
#define VHWORD  volatile short

/******************************************************************************
*
* Definitions of Parameter RAM entries for each peripheral and mode
*
******************************************************************************/

/*---------------------------------------------------------------------------*/
/*                      HDLC parameter RAM (SCC)                                       */
/*---------------------------------------------------------------------------*/

struct hdlc_pram 

{
       
   /*-------------------*/
   /* SCC parameter RAM */
   /*-------------------*/
   
   UHWORD   rbase;      /* RX BD base address */
   UHWORD   tbase;      /* TX BD base address */
   UBYTE       rfcr;           /* Rx function code */
   UBYTE       tfcr;           /* Tx function code */
   UHWORD   mrblr;      /* Rx buffer length */
   UWORD       rstate;      /* Rx internal state */
   UWORD       rptr;           /* Rx internal data pointer */
   UHWORD   rbptr;      /* rb BD Pointer */
   UHWORD   rcount;     /* Rx internal byte count */
   UWORD       rtemp;       /* Rx temp */
   UWORD       tstate;      /* Tx internal state */
   UWORD       tptr;           /* Tx internal data pointer */
   UHWORD   tbptr;      /* Tx BD pointer */
   UHWORD   tcount;     /* Tx byte count */
   UWORD       ttemp;       /* Tx temp */
   UWORD       rcrc;           /* temp receive CRC */
   UWORD       tcrc;           /* temp transmit CRC */
   
   /*-----------------------------*/
   /* HDLC specific parameter RAM */
   /*-----------------------------*/

   UBYTE       RESERVED1[4];    /* Reserved area */
   UWORD       c_mask;          /* CRC constant */
   UWORD       c_pres;          /* CRC preset */
   UHWORD   disfc;          /* discarded frame counter */
   UHWORD   crcec;          /* CRC error counter */
   UHWORD   abtsc;          /* abort sequence counter */
   UHWORD   nmarc;          /* nonmatching address rx cnt */
   UHWORD   retrc;          /* frame retransmission cnt */
   UHWORD   mflr;              /* maximum frame length reg */
   UHWORD   max_cnt;           /* maximum length counter */
   UHWORD   rfthr;          /* received frames threshold */
   UHWORD   rfcnt;          /* received frames count */
   UHWORD   hmask;          /* user defined frm addr mask */
   UHWORD   haddr1;         /* user defined frm address 1 */
   UHWORD   haddr2;         /* user defined frm address 2 */
   UHWORD   haddr3;         /* user defined frm address 3 */
   UHWORD   haddr4;         /* user defined frm address 4 */
   UHWORD   tmp;               /* temp */
   UHWORD   tmp_mb;         /* temp */
};


/*-------------------------------------------------------------------------*/
/*                   ASYNC HDLC parameter RAM (SCC)                              */
/*-------------------------------------------------------------------------*/

struct async_hdlc_pram 

{
       
   /*-------------------*/
   /* SCC parameter RAM */
   /*-------------------*/

   UHWORD   rbase;      /* RX BD base address */
   UHWORD   tbase;      /* TX BD base address */
   UBYTE       rfcr;           /* Rx function code */
   UBYTE       tfcr;           /* Tx function code */
   UHWORD   mrblr;      /* Rx buffer length */
   UWORD       rstate;      /* Rx internal state */
   UWORD       rptr;           /* Rx internal data pointer */
   UHWORD   rbptr;      /* rb BD Pointer */
   UHWORD   rcount;     /* Rx internal byte count */
   UWORD       rtemp;       /* Rx temp */
   UWORD       tstate;      /* Tx internal state */
   UWORD       tptr;           /* Tx internal data pointer */
   UHWORD   tbptr;      /* Tx BD pointer */
   UHWORD   tcount;     /* Tx byte count */
   UWORD    ttemp;      /* Tx temp */
   UWORD       rcrc;           /* temp receive CRC */
   UWORD    tcrc;          /* temp transmit CRC */
         
   /*-----------------------------------*/
   /* ASYNC HDLC specific parameter RAM */
   /*-----------------------------------*/

   UBYTE       RESERVED2[4];    /* Reserved area */
   UWORD       c_mask;          /* CRC constant */
   UWORD       c_pres;          /* CRC preset */
   UHWORD   bof;               /* begining of flag character */
   UHWORD   eof;               /* end of flag character */
   UHWORD   esc;               /* control escape character */
   UBYTE       RESERVED3[4];    /* Reserved area */
   UHWORD   zero;              /* zero */
   UBYTE       RESERVED4[2];    /* Reserved area */
   UHWORD   rfthr;          /* received frames threshold */
   UBYTE       RESERVED5[4];    /* Reserved area */
   UWORD       txctl_tbl;       /* Tx ctl char mapping table */
   UWORD       rxctl_tbl;       /* Rx ctl char mapping table */
   UHWORD   nof;               /* Number of opening flags */
};


/*--------------------------------------------------------------------------*/
/*                    UART parameter RAM (SCC)                                     */
/*--------------------------------------------------------------------------*/

/*----------------------------------------*/
/* bits in uart control characters table  */
/*----------------------------------------*/

#define CC_INVALID  0x8000      /* control character is valid */
#define CC_REJ      0x4000      /* don't store char in buffer */
#define CC_CHAR     0x00ff      /* control character */

/*------*/
/* UART */
/*------*/

struct uart_pram 

{
   /*-------------------*/
   /* SCC parameter RAM */
   /*-------------------*/

   UHWORD   rbase;      /* RX BD base address */
   UHWORD   tbase;      /* TX BD base address */
   UBYTE       rfcr;           /* Rx function code */
   UBYTE       tfcr;           /* Tx function code */
   UHWORD   mrblr;      /* Rx buffer length */
   UWORD       rstate;      /* Rx internal state */
   UWORD       rptr;           /* Rx internal data pointer */
   UHWORD   rbptr;      /* rb BD Pointer */
   UHWORD   rcount;     /* Rx internal byte count */
   UWORD       rx_temp;    /* Rx temp */
   UWORD       tstate;      /* Tx internal state */
   UWORD       tptr;           /* Tx internal data pointer */
   UHWORD   tbptr;      /* Tx BD pointer */
   UHWORD   tcount;     /* Tx byte count */
   UWORD       ttemp;       /* Tx temp */
   UWORD       rcrc;           /* temp receive CRC */
   UWORD       tcrc;           /* temp transmit CRC */

   /*------------------------------*/
   /*   UART specific parameter RAM  */
   /*------------------------------*/

   UBYTE       RESERVED6[8];    /* Reserved area */
   UHWORD   max_idl;           /* maximum idle characters */
   UHWORD   idlc;              /* rx idle counter (internal) */
   UHWORD   brkcr;          /* break count register */

   UHWORD   parec;          /* Rx parity error counter */
   UHWORD   frmec;          /* Rx framing error counter */
   UHWORD   nosec;          /* Rx noise counter */
   UHWORD   brkec;          /* Rx break character counter */
   UHWORD   brkln;          /* Reaceive break length */
                                           
   UHWORD   uaddr1;         /* address character 1 */
   UHWORD   uaddr2;         /* address character 2 */
   UHWORD   rtemp;          /* temp storage */
   UHWORD   toseq;          /* Tx out of sequence char */
   UHWORD   cc[8];          /* Rx control characters */
   UHWORD   rccm;              /* Rx control char mask */
   UHWORD   rccr;              /* Rx control char register */
   UHWORD   rlbc;              /* Receive last break char */
};


/*---------------------------------------------------------------------------
*                    BISYNC parameter RAM (SCC)
*--------------------------------------------------------------------------*/

struct bisync_pram 

{
   /*-------------------*/
   /* SCC parameter RAM */
   /*-------------------*/

   UHWORD   rbase;      /* RX BD base address */
   UHWORD   tbase;      /* TX BD base address */
   UBYTE       rfcr;           /* Rx function code */
   UBYTE       tfcr;           /* Tx function code */
   UHWORD   mrblr;      /* Rx buffer length */
   UWORD       rstate;      /* Rx internal state */
   UWORD       rptr;           /* Rx internal data pointer */
   UHWORD   rbptr;      /* rb BD Pointer */
   UHWORD   rcount;     /* Rx internal byte count */
   UWORD       rtemp;       /* Rx temp */
   UWORD       tstate;      /* Tx internal state */
   UWORD       tptr;           /* Tx internal data pointer */
   UHWORD   tbptr;      /* Tx BD pointer */
   UHWORD   tcount;     /* Tx byte count */
   UWORD       ttemp;       /* Tx temp */
   UWORD       rcrc;           /* temp receive CRC */
   UWORD       tcrc;           /* temp transmit CRC */

   /*--------------------------------*/
   /*   BISYNC specific parameter RAM */
   /*--------------------------------*/

   UBYTE       RESERVED7[4];    /* Reserved area */
   UWORD       crcc;               /* CRC Constant Temp Value */
   UHWORD   prcrc;          /* Preset Receiver CRC-16/LRC */
   UHWORD   ptcrc;          /* Preset Transmitter CRC-16/LRC */
   UHWORD   parec;          /* Receive Parity Error Counter */
   UHWORD   bsync;          /* BISYNC SYNC Character */
   UHWORD   bdle;              /* BISYNC DLE Character */
   UHWORD   cc[8];          /* Rx control characters */
   UHWORD   rccm;              /* Receive Control Character Mask */
};


/*-------------------------------------------------------------------------*/
/*             Transparent mode parameter RAM (SCC)                        */
/*-------------------------------------------------------------------------*/

struct transparent_pram 

{
   /*--------------------*/
   /*   SCC parameter RAM */
   /*--------------------*/

   UHWORD   rbase;      /* RX BD base address */
   UHWORD   tbase;      /* TX BD base address */
   UBYTE       rfcr;           /* Rx function code */
   UBYTE       tfcr;           /* Tx function code */
   UHWORD   mrblr;      /* Rx buffer length */
   UWORD       rstate;      /* Rx internal state */
   UWORD       rptr;           /* Rx internal data pointer */
   UHWORD   rbptr;      /* rb BD Pointer */
   UHWORD   rcount;     /* Rx internal byte count */
   UWORD       rtemp;       /* Rx temp */
   UWORD       tstate;      /* Tx internal state */
   UWORD       tptr;           /* Tx internal data pointer */
   UHWORD   tbptr;      /* Tx BD pointer */
   UHWORD   tcount;     /* Tx byte count */
   UWORD       ttemp;       /* Tx temp */
   UWORD       rcrc;           /* temp receive CRC */
   UWORD       tcrc;           /* temp transmit CRC */

   /*-------------------------------------*/
   /*   TRANSPARENT specific parameter RAM */
   /*-------------------------------------*/

   UWORD    crc_p;      /* CRC Preset */
   UWORD    crc_c;      /* CRC constant */
};


/*-------------------------------------------------------------------------*/ 
/*                    Ethernet parameter RAM (SCC)                               */
/*-------------------------------------------------------------------------*/