📄 main.lst
字号:
829 03b8 0000 nop
337:main.c **** nop();
831 .LM114:
832 03ba 0000 nop
338:main.c **** nop();
834 .LM115:
835 03bc 0000 nop
339:main.c **** Set_Bit(PORTC,Write);
837 .LM116:
838 /* #NOAPP */
839 03be 8091 3500 lds r24,53
840 03c2 8068 ori r24,lo8(-128)
841 03c4 8093 3500 sts 53,r24
842 /* epilogue: frame size=2 */
843 03c8 2296 adiw r28,2
844 03ca 0FB6 in __tmp_reg__,__SREG__
845 03cc F894 cli
846 03ce DEBF out __SP_H__,r29
847 03d0 0FBE out __SREG__,__tmp_reg__
848 03d2 CDBF out __SP_L__,r28
849 03d4 DF91 pop r29
850 03d6 CF91 pop r28
851 03d8 0895 ret
852 /* epilogue end (size=9) */
853 /* function WriteData size 59 (40) */
855 .Lscope7:
859 .global WriteReg
861 WriteReg:
340:main.c **** }
341:main.c **** /************************************************************
342:main.c **** *函数名称:void WriteReg(byte byAddr,byte byData) *
343:main.c **** *用途:写寄存器:寄存器地址，数据,无返回值 *
344:main.c **** ************************************************************/
345:main.c **** void WriteReg(byte byAddr,byte byData)
346:main.c **** {
863 .LM117:
864 /* prologue: frame size=2 */
865 03da CF93 push r28
866 03dc DF93 push r29
867 03de CDB7 in r28,__SP_L__
868 03e0 DEB7 in r29,__SP_H__
869 03e2 2297 sbiw r28,2
870 03e4 0FB6 in __tmp_reg__,__SREG__
871 03e6 F894 cli
872 03e8 DEBF out __SP_H__,r29
873 03ea 0FBE out __SREG__,__tmp_reg__
874 03ec CDBF out __SP_L__,r28
875 /* prologue end (size=10) */
876 03ee 8983 std Y+1,r24
877 03f0 6A83 std Y+2,r22
347:main.c **** byData=ReversalData(byData);
879 .LM118:
880 03f2 8A81 ldd r24,Y+2
881 03f4 0E94 0000 call ReversalData
882 03f8 8A83 std Y+2,r24
348:main.c **** RegAddrChangePhysics(byAddr);
884 .LM119:
885 03fa 8981 ldd r24,Y+1
886 03fc 0E94 0000 call RegAddrChangePhysics
349:main.c **** DDRA=0xff;
888 .LM120:
889 0400 8FEF ldi r24,lo8(-1)
890 0402 8093 3A00 sts 58,r24
350:main.c **** WDataL=byData;
892 .LM121:
893 0406 8A81 ldd r24,Y+2
894 0408 8093 3B00 sts 59,r24
351:main.c **** Clr_Bit(PORTC,Write);
896 .LM122:
897 040c 9FE7 ldi r25,lo8(127)
898 040e 8091 3500 lds r24,53
899 0412 8923 and r24,r25
900 0414 8093 3500 sts 53,r24
352:main.c **** nop();
902 .LM123:
903 /* #APP */
904 0418 0000 nop
353:main.c **** nop();
906 .LM124:
907 041a 0000 nop
354:main.c **** nop();
909 .LM125:
910 041c 0000 nop
355:main.c **** nop();
912 .LM126:
913 041e 0000 nop
356:main.c **** Set_Bit(PORTC,Write);
915 .LM127:
916 /* #NOAPP */
917 0420 8091 3500 lds r24,53
918 0424 8068 ori r24,lo8(-128)
919 0426 8093 3500 sts 53,r24
920 /* epilogue: frame size=2 */
921 042a 2296 adiw r28,2
922 042c 0FB6 in __tmp_reg__,__SREG__
923 042e F894 cli
924 0430 DEBF out __SP_H__,r29
925 0432 0FBE out __SREG__,__tmp_reg__
926 0434 CDBF out __SP_L__,r28
927 0436 DF91 pop r29
928 0438 CF91 pop r28
929 043a 0895 ret
930 /* epilogue end (size=9) */
931 /* function WriteReg size 53 (34) */
933 .Lscope8:
935 .global WaitBSY
937 WaitBSY:
357:main.c **** }
358:main.c **** /************************************************************
359:main.c **** *函数名称:byte WaitBSY(void) *
360:main.c **** *用途:等待BSY信号 *
361:main.c **** ************************************************************/
362:main.c **** byte WaitBSY(void)
363:main.c **** {
939 .LM128:
940 /* prologue: frame size=0 */
941 043c CF93 push r28
942 043e DF93 push r29
943 0440 CDB7 in r28,__SP_L__
944 0442 DEB7 in r29,__SP_H__
945 /* prologue end (size=4) */
946 .L33:
364:main.c **** //byte timeOut=0;
365:main.c **** do
366:main.c **** {
367:main.c **** HDstate=ReadReg(_Status_AND_Command);
948 .LM129:
949 0444 87E0 ldi r24,lo8(7)
950 0446 0E94 0000 call ReadReg
951 044a 8093 0000 sts HDstate,r24
368:main.c **** //timeOut++;
369:main.c **** //if(timeOut>=254)
370:main.c **** //return(0xff); //超时
371:main.c **** }while(BSY);
953 .LM130:
954 044e 8091 0000 lds r24,HDstate
955 0452 8823 tst r24
956 0454 0CF4 brge .L34
958 .LM131:
959 0456 F6CF rjmp .L33
960 .L34:
372:main.c **** return(1);
962 .LM132:
963 0458 81E0 ldi r24,lo8(1)
964 045a 90E0 ldi r25,hi8(1)
965 /* epilogue: frame size=0 */
966 045c DF91 pop r29
967 045e CF91 pop r28
968 0460 0895 ret
969 /* epilogue end (size=3) */
970 /* function WaitBSY size 19 (12) */
972 .Lscope9:
974 .global WaitDRQ
976 WaitDRQ:
373:main.c **** }
374:main.c **** /************************************************************
375:main.c **** *函数名称:byte WaitDRQ(void) *
376:main.c **** *用途:等待DRQ信号 *
377:main.c **** ************************************************************/
378:main.c **** byte WaitDRQ(void)
379:main.c **** {
978 .LM133:
979 /* prologue: frame size=0 */
980 0462 CF93 push r28
981 0464 DF93 push r29
982 0466 CDB7 in r28,__SP_L__
983 0468 DEB7 in r29,__SP_H__
984 /* prologue end (size=4) */
985 .L37:
380:main.c **** //byte timeOut=0;
381:main.c **** do
382:main.c **** {
383:main.c **** HDstate=ReadReg(_Status_AND_Command);
987 .LM134:
988 046a 87E0 ldi r24,lo8(7)
989 046c 0E94 0000 call ReadReg
990 0470 8093 0000 sts HDstate,r24
384:main.c **** //timeOut++;
385:main.c **** //if(timeOut>=254)
386:main.c **** //return(0xff); //超时
387:main.c **** }while(!DRQ);
992 .LM135:
993 0474 8091 0000 lds r24,HDstate
994 0478 9927 clr r25
995 047a 9695 lsr r25
996 047c 8795 ror r24
997 047e 9695 lsr r25
998 0480 8795 ror r24
999 0482 9695 lsr r25
1000 0484 8795 ror r24
1001 0486 8170 andi r24,lo8(1)
1002 0488 9070 andi r25,hi8(1)
1003 048a 0097 sbiw r24,0
1004 048c 09F4 brne .L38
1006 .LM136:
1007 048e EDCF rjmp .L37
1008 .L38:
388:main.c **** return(1);
1010 .LM137:
1011 0490 81E0 ldi r24,lo8(1)
1012 0492 90E0 ldi r25,hi8(1)
1013 /* epilogue: frame size=0 */
1014 0494 DF91 pop r29
1015 0496 CF91 pop r28
1016 0498 0895 ret
1017 /* epilogue end (size=3) */
1018 /* function WaitDRQ size 28 (21) */
1020 .Lscope10:
1023 .global RegAddrChangePhysics
1025 RegAddrChangePhysics:
389:main.c **** }
390:main.c **** /************************************************************
391:main.c **** *函数名称:void RegAddrChangePhysics(byte byRegAddr) *
392:main.c **** *用途:把寄存器地址转化为物理接口 *
393:main.c **** ************************************************************/
394:main.c **** void RegAddrChangePhysics(byte byRegAddr)
395:main.c **** {
1027 .LM138:
1028 /* prologue: frame size=3 */
1029 049a CF93 push r28
1030 049c DF93 push r29
1031 049e CDB7 in r28,__SP_L__
1032 04a0 DEB7 in r29,__SP_H__
1033 04a2 2397 sbiw r28,3
1034 04a4 0FB6 in __tmp_reg__,__SREG__
1035 04a6 F894 cli
1036 04a8 DEBF out __SP_H__,r29
1037 04aa 0FBE out __SREG__,__tmp_reg__
1038 04ac CDBF out __SP_L__,r28
1039 /* prologue end (size=10) */
1040 04ae 8983 std Y+1,r24
396:main.c **** Clr_Bit(PORTC,CS0);
1042 .LM139:
1043 04b0 8091 3500 lds r24,53
1044 04b4 8E7F andi r24,lo8(-2)
1045 04b6 8093 3500 sts 53,r24
397:main.c **** Set_Bit(PORTC,CS1);
1047 .LM140:
1048 04ba 8091 3500 lds r24,53
1049 04be 8260 ori r24,lo8(2)
1050 04c0 8093 3500 sts 53,r24
398:main.c **** switch(byRegAddr)
1052 .LM141:
1053 04c4 8981 ldd r24,Y+1
1054 04c6 282F mov r18,r24
1055 04c8 3327 clr r19
1056 04ca 2A83 std Y+2,r18
1057 04cc 3B83 std Y+3,r19
1058 04ce 8A81 ldd r24,Y+2
1059 04d0 9B81 ldd r25,Y+3
1060 04d2 8330 cpi r24,3
1061 04d4 9105 cpc r25,__zero_reg__
1062 04d6 09F4 brne .+2
1063 04d8 61C0 rjmp .L45
1065 .LM142:
1066 04da 2A81 ldd r18,Y+2
1067 04dc 3B81 ldd r19,Y+3
1068 04de 2430 cpi r18,4
1069 04e0 3105 cpc r19,__zero_reg__
1070 04e2 84F4 brge .L50
1071 04e4 8A81 ldd r24,Y+2
1072 04e6 9B81 ldd r25,Y+3
1073 04e8 8130 cpi r24,1
1074 04ea 9105 cpc r25,__zero_reg__
1075 04ec A9F1 breq .L43
1076 04ee 2A81 ldd r18,Y+2
1077 04f0 3B81 ldd r19,Y+3
1078 04f2 2230 cpi r18,2
1079 04f4 3105 cpc r19,__zero_reg__
1080 04f6 0CF0 brlt .+2
1081 04f8 40C0 rjmp .L44
1082 04fa 8A81 ldd r24,Y+2
1083 04fc 9B81 ldd r25,Y+3
1084 04fe 0097 sbiw r24,0
1085 0500 D1F0 breq .L42
1086 0502 9CC0 rjmp .L40
1087 .L50:
1088 0504 2A81 ldd r18,Y+2
1089 0506 3B81 ldd r19,Y+3
1090 0508 2530 cpi r18,5
1091 050a 3105 cpc r19,__zero_reg__
1092 050c 09F4 brne .+2
1093 050e 67C0 rjmp .L47
1094 0510 8A81 ldd r24,Y+2
1095 0512 9B81 ldd r25,Y+3
1096 0514 8530 cpi r24,5
1097 0516 9105 cpc r25,__zero_reg__
1098 0518 0CF4 brge .+2
1099 051a 51C0 rjmp .L46
1100 051c 2A81 ldd r18,Y+2
1101 051e 3B81 ldd r19,Y+3
1102 0520 2630 cpi r18,6
1103 0522 3105 cpc r19,__zero_reg__
1104 0524 09F4 brne .+2
1105 0526 6BC0 rjmp .L48
1106 0528 8A81 ldd r24,Y+2
1107 052a 9B81 ldd r25,Y+3
1108 052c 8730 cpi r24,7
1109 052e 9105 cpc r25,__zero_reg__
1110 0530 09F4 brne .+2
1111 0532 75C0 rjmp .L49
1112 0534 83C0 rjmp .L40
1113 .L42:
399:main.c **** {
400:main.c **** case _Data:
401:main.c **** Clr_Bit(PORTD,DA0);
1115 .LM143:
1116 0536 8091 3200 lds r24,50
1117 053a 8F7D andi r24,lo8(-33)
1118 053c 8093 3200 sts 50,r24
402:main.c **** Clr_Bit(PORTD,DA1);
1120 .LM144:
1121 0540 8091 3200 lds r24,50
1122 0544 8F7B andi r24,lo8(-65)
1123 0546 8093 3200 sts 50,r24
403:main.c **** Clr_Bit(PORTD,DA2);
1125 .LM145:
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