dp83815.h

三星2410的BSP开发包

#define DP83815_cmdsts_Rx_RXO		(1<<25)	//RXO Receive Overrun Set to 1 by DP83815 to indicate that a receive overrun condition occurred. RXA will also be set.
#define DP83815_cmdsts_Rx_DEST		0x1800000 //Destination Class. Bits 24-23. When the receive filter is enabled, these bits will indicate the destination address class as follows:
											//00 - Packet was rejected
											//01 - Destination is a Unicast address
											//10 - Destination is a Multicast address
											//11 - Destination is a Broadcast address
											//If the Receive Filter is enabled, 00 indicates that the packet was rejected. Normally packets that are rejected do not cause any bus activity, nor do they consume receive descriptors. However, this
											//condition could occur if the packet is rejected by the Receive Filter later in the packet than the receive drain threshold (RXCFG:DRTH). Note: The DEST bits may not represent a correct DA class for runt
											//packets received with less than 6 bytes.

#define DP83815_cmdsts_Rx_LONG 		(1<<22)	//Too Long Packet Received.  If RXCFG:ALP=0, this flag indicates that the size of the receive packet exceeded 1518 bytes. If RXCFG:ALP=1, this flag indicates that the size of the receive packet exceeded 2046 bytes.
#define DP83815_cmdsts_Rx_RUNT		(1<<21)	//Runt Packet Received. The size of the receive packet was less than 64 bytes (inc. CRC).
#define DP83815_cmdsts_Rx_ISE		(1<<20)	//Invalid Symbol Error (100 Mb/s only). An invalid symbol was encountered during the reception of this packet.
#define DP83815_cmdsts_Rx_CRCE		(1<<19)	//CRC Error The CRC appended to the end of this packet was invalid.
#define DP83815_cmdsts_Rx_FAE		(1<<18)	//Frame Alignment Error The packet did not contain an integral number of octets.
#define DP83815_cmdsts_Rx_LBP		(1<<17)	//Loopback Packet The packet is the result of a loopback transmission.
#define DP83815_cmdsts_Rx_COL		(1<<16)	//Collision Activity The receive packet had a collision during reception.
#define DP83815_cmdsts_Rx_ANYERROR	(DP83815_cmdsts_Rx_RXO|DP83815_cmdsts_Rx_LONG|DP83815_cmdsts_Rx_RUNT|DP83815_cmdsts_Rx_ISE|DP83815_cmdsts_Rx_CRCE|DP83815_cmdsts_Rx_FAE|DP83815_cmdsts_Rx_COL)
//rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr

// Bits 15-12 are reserved by National Semi.

/* The 12 low order bits of cmdsts hold the size of the DP83815FrameDescriptor structure in bytes.  It would be better
to use the "sizeof()" operator for further development rather than reading these bits, 
but the hardware needs to know this value and exactly where to find it.  Note that this limits the size of the descriptor 
to 4096 bytes.*/

#define DP83815_cmdsts_SIZE	(0x0FFF)		//	Low order 12 bits  (11-0) hold size of DP83815FrameDescriptor structure.
// ------------End of DP83815FrameDescriptor definitions--------------------------------------------------------------------------------


// ---------Begin DP83815 PCI Configuration register  definitions---------------------------------------------------
#define DP_PCI_CFGID	(0x0) 

#define DP83815_CFGCS	(0x04) 
/* The CFGCS register has two parts. The upper 16-bits (31-16) are devoted to device status. A status bit is reset whenever
the register is written, and the corresponding bit location is a 1. The lower 16-bits (15-0) are devoted to command and are
used to configure and control the device.*/
//TODO: There are many currently unrepresented bits in this register.  See if any more are needed for a debug driver.
//ValueMasks:
#define DP83815_cfgcs_BMEN	(1<<2)	//Bus Master Enable.  When set, DP83815 is allowed to act as a PCI bus master. When reset, DP83815 is prohibited from acting as a PCI bus master. 
#define DP83815_cfgcs_MSEN	(1<<1)	//Memory Space Address Enable.  When set, DP83815 responds to memory space accesses. When reset, DP83815 ignores memory space accesses.
#define DP83815_cfgcs_IOSEN	(1<<0)	//I/O Space Access Enable.  When set, DP83815 responds to I/O space accesses. When reset, DP83815 ignores I/O space accesses.
//-------------End DP83815 PCI Configuration register  definitions -------------------------------------------------



// ---------Begin DP83815 Operational register  definitions---------------------------------------------------
#define DP_OPS_CR			(0x00)
/* Command Register.  This register is used for issuing commands to DP83815. These commands are issued by setting the 
corresponding bits for the function. A global software reset along with individual reset and enable/disable for 
transmitter and receiver are provided here.*/
// ValueMasks:
// bits 31-9 are unused.
#define DP_OPS_cr_RST			(1<<8) /*  Reset.  Set to 1 to force the DP83815 to a soft reset state which disables the 
											transmitter and receiver, reinitializes the FIFOs, and resets all affected 
											registers to their soft reset state. This operation implies both a TXR and a RXR.
											This bit will read back a 1 during the reset operation, and be cleared to 0 by 
											the hardware when the reset operation is complete. EEPROM configuration information
											is not loaded here. */
#define DP_OPS_cr_SWI			(1<<7) //   Software Interrupt.  Setting this bit to a 1 forces the DP83815 to generate a hardware interrupt. This interrupt is mask-able via the IMR.
// bit 6 is unused
#define DP_OPS_cr_RXR			(1<<5) /*  Receiver Reset.  When set to a 1, this bit causes the current packet reception to be aborted, the receive data and status
											FIFOs to be flushed, and the receive state machine to enter the idle state 
											(RXE goes to 0). This is a write-only bit and is always read back as 0. */
#define DP_OPS_cr_TXR			(1<<4) /*  Transmit Reset. When set to a 1, this bit causes the current transmission to 
											be aborted, the transmit data and status FIFOs to be flushed, and the transmit
											state machine to enter the idle state (TXE goes to 0). This is a write-only bit
											and is always read back as 0. */
#define DP_OPS_cr_RXD			(1<<3) /*  Receiver Disable.  Disable the receive state machine after any current packets
											in progress. When this operation has been completed the RXE bit will be cleared
											to 0. This is a write-only bit and is always read back as 0. The driver should
											not set both RXD and RXE in the same write, the RXE will be ignored, and RXD 
											will have precedence.*/
#define DP_OPS_cr_RXE			(1<<2) /*  Receiver Enable.  When set to a 1, and the receive state machine is idle, then
											the receive machine becomes active. This bit will read back as a 1 whenever 
											the receive state machine is active. After initial power-up, software must
											insure that the receiver has completely reset before setting this bit (See ISR:RXRCMP). */
#define DP_OPS_cr_TXD			(1<<1) /*  Transmit Disable.  When set to a 1, halts the transmitter after the completion 
											of the current packet. This is a write-only bit and is always read back as 0. 
											The driver should not set both TXD and TXE in the same write, the TXE will be 
											ignored, and TXD will have precedence. */
#define DP_OPS_cr_TXE			(1<<0) /*  Transmit Enable.  When set to a 1, and the transmit state machine is idle, then
											the transmit state machine becomes active.  This bit will read back as a 1 
											whenever the transmit state machine is active. After initial power-up, 
											software must insure that the transmitter has completely reset before setting 
											this bit (See ISR:TXRCMP).*/
//-------------------------------------
#define DP_OPS_CFG			(0x04)  
/*Configuration and Media Status Register.  This register allows configuration of a variety of device and phy options, 
and provides phy status information. */
//ValueMasks:
#define DP_OPS_cfg_LNKSTS	(1<<31)  //Link status of the internal phy. Asserted when link is good. RO
#define DP_OPS_cfg_SPEED100	(1<<30)  //Speed 100 Mb/s indicator for internal phy. Asserted when speed is set or has negotiated to 100 Mb/s.  De-asserted when speed has been set or negotiated to 10 Mb/s. RO
#define DP_OPS_cfg_ANEG_DN	(1<<28)	// Auto-negotiation done indicator from internal phy. Asserted when auto-negotiation process has completed or is not active. RO
#define DP_OPS_cfg_POL		(1<<28)  //Twisted pair polarity indicator for internal phy. Asserted when operating and 10 Mb/s and the polarity has been detected as reversed. De-asserted when polarity is normal or phy is operating at 100 Mb/s. RO
#define DP_OPS_cfg_ANEG_SEL	(0x0000E000)// Auto-negotiation Select.These bits are loaded from EEPROM at power-up and are used to define the default state of the internal phy auto-negotiation logic. R/W These bits are encoded as follows:
										// 000 Auto-negotiation disabled, force 10 Mb/s half duplex
										// 010 Auto-negotiation disabled, force 100 Mb/s half duplex
										// 100 Auto-negotiation disabled, force 10 Mb/s full duplex
										// 110 Auto-negotiation disabled, force 100 Mb/s full duplex
										// 001 Auto-negotiation enabled, advertise 10 Mb/s half & full duplex
										// 011 Auto-negotiation enabled, advertise 10/100 Mb/s half duplex
										// 101 Auto-negotiation enabled, advertise 100 Mb/s half & full duplex
										// 111 Auto-negotiation enabled, advertise 10/100 Mb/s half & full duplex  <-- This is what we will init.
#define DP_OPS_cfg_PESEL	(1<<3)   /* Parity Error Detection Action.  This bit controls the assertion of SERR when a 
										data parity error is detected while the DP83815 is acting as the bus master. When 
										set, parity errors will not result in the assertion of SERR. When reset, parity
										errors will result in the assertion of SERR, indicating a system error. This bit 
										should be set to a one by software if the driver can handle recovery from and 
										reporting of data parity errors. R/W */
//-------------------------------------
#define DP_OPS_PTSCR			(0x000C) 
/* PCI Test Control Register */
//ValueMasks:
#define DP_OPS_ptscr_EELOAD_EN	(1<<2)  /* Enable EEPROM Load.  This bit is set to a 1 to manually initiate a load of 
											configuration information from EEPROM. A 1 is returned while the configuration 
											load from EEPROM is active (approx. 1500 us). R/W */
//-------------------------------------
#define DP_OPS_ISR				(0x0010)
/*Interrupt Status Register.  This register indicates the source of an interrupt when the INTA pin goes active. Enabling 
the corresponding bits in the Interrupt Mask Register (IMR) allows bits in this register to produce an interrupt. When 
an interrupt is active, one or more bits in this register are set to a