dp83815.h

三星2410的BSP开发包

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:  DP83815.h

Author:  Kirk Gremillion (kirkgrem)

Abstract:  
    Definitions for register access of National Semiconductor
	DP83815 MACPHYter integrated ethernet device.
    
    
Notes: 
	There are more definitions here than are used in the driver itself.  Much of the comments come straight
	from the public DP83815 documents with additional application notes from kirkgrem.

   
--*/


#define BUFFSIZE  1520 // Size (length) of Buffer allocated to each Tx/Rx descriptor.

// Macros all defined here
//#define PRINTF(cond, printf_exp)   ((void)((cond)?(EdbgOutputDebugString printf_exp) : 0))
#define PRINTF(cond, printf_exp)


// IO macros for Operational Registers.  Note that Tag, equates to offset in all device-specific register definitions, 
//and ValueMask equates to bitmasks for those registers.
#define DPWriteLong(Tag,ValueMask,Value)    DP_WRITE_PORT_ULONG((volatile PULONG)(MyDP.UsedAddr+Tag),(Value & ValueMask))
#define DPReadLong(Tag, ValueMask)        (ValueMask & DP_READ_PORT_ULONG((volatile PULONG)(MyDP.UsedAddr+Tag)))
//DPModifyLong() is a function in DP83815.c

#define DP_allbits				(0xFFFFFFFF)  // bit ValueMask to get all of the bits in a register for local manipulation.

/* ---------Begin DP83815FrameDescriptor definitions--------------------------------------------------------------------
Descriptors are identical in form and size between Tx and Rx.  Some bits are used differently from Tx to Rx.  Read below.
  
	Table 5-1 DP83815 Descriptor Format (from DP83815 public documentation)
Offset	Tag		Description
0000h	link	32-bit "link" field to the next descriptor in the linked list. 
				Bits 1-0 must be 0, as descriptors must be aligned on 32-bit boundaries.

0004h	cmdsts	32-bit Command/Status Field (bit-encoded).

0008h	bufptr	32-bit pointer to the first fragment or buffer. In transmit descriptors, 
				the buffer can begin on any byte boundary. In receive descriptors, the buffer 
				must be aligned on a 32-bit boundary.

So I will define a corresponding Structure below.*/

typedef struct _DP83815FrameDescriptor
{
	struct _DP83815FrameDescriptor*	link;		// 32-bit "link" field to the next descriptor in the linked list. Physical Address. 
	DWORD	cmdsts;		// 32-bit Command/Status Field (bit-encoded).
	DWORD	bufptr;	    // 32-bit pointer to the buffer. (should not have fragments if buffer large enough for entire frame)
} DP83815FrameDescriptor,*pDP83815FrameDescriptor;

/*  In the above structure, the cmdsts field has the following definitions.  Just  'AND'
	these with "myDP83815FrameDescriptor->cmdsts" to get a boolean result.*/


#define DP83815_cmdsts_OWN		(1<<31) //		Descriptor Ownership. Set to 1 by the data producer of the descriptor
										// to transfer ownership to the data consumer of the descriptor. Set to
										// 0 by the data consumer of the descriptor to return ownership to the
										// data producer of the descriptor. For transmit descriptors, this 
										// driver is the data producer, and the DP83815 is the data consumer. 
										// For receive descriptors, the DP83815 is the data producer, and this
										// driver is the data consumer.

#define DP83815_cmdsts_MORE	(1<<30)		//		More descriptors. Set to 1 to indicate that this is NOT the last 
										// descriptor in a packet(there are MORE to follow). When 0, this 
										// descriptor is the last descriptor in a packet. Completion status 
										// bits are only valid when this bit is zero.
										// Note: in TX descriptors, the DP83815 clears the MORE bit when returning
										// control, in RX descriptors it clears the MORE bit if there are no more descriptors
										// associated with this frame, however, it EXPECTS the MORE bit to be SET in a 
										// currently unused descriptor in the ring.  If this bit is not set, the DP83815 assumes
										// the OWN bit is in error, and skips to the next descriptor.  

#define DP83815_cmdsts_INTR	(1<<29)		//		Interrupt. Set to 1 by software to request a "descriptor interrupt" 
										// when DP83815 transfers the ownership of this descriptor back to
										// software.

#define DP83815_cmdsts_SUPCRC	(1<<28)	//		Suppress CRC /Include CRC.  In transmit descriptors, this indicates
										// that CRC should not be appended by the MAC. On receives, this bit is 
										// always set, as the CRC is always copied to the end of the buffer by the hardware.

#define DP83815_cmdsts_OK		(1<<27)	//			Packet (Frame) OK. In the last descriptor in a packet (frame), this bit 
										// indicates that the packet (frame) was either sent or received successfully.


// Tx/Rx specific bits.  Bits 26-16 of cmdsts have different meaning if the descriptor is for TX or Rx.
// Tx specific TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT
#define DP83815_cmdsts_Tx_TXA		(1<<26)	//Transmit Abort. Transmission of this packet (frame) was aborted.
#define DP83815_cmdsts_Tx_TFU		(1<<25)	//Transmit FIFO Underrun. Transmit FIFO was exhausted during the transmission of this packet.
#define DP83815_cmdsts_Tx_CRS		(1<<24)	//Carrier Sense Lost. Carrier was lost during the transmission of this packet. This condition is not reported if TXCFG:CSI is set.
#define DP83815_cmdsts_Tx_TD		(1<<23)	//Transmit Deferred. Transmission of this packet was deferred.
#define DP83815_cmdsts_Tx_ED		(1<<22)	//Excessive Deferral The length of deferral during the transmission of this packet was excessive (> 3.2 ms), indicating transmission failure.
#define DP83815_cmdsts_Tx_OWC 		(1<<21)	//Out of Window Collision.  The MAC encountered an "out of window" collision during the transmission of this packet.
#define DP83815_cmdsts_Tx_EC 		(1<<20)	//Excessive Collisions. The number of collisions during the transmission of this packet was excessive, indicating transmission failure.
											//If TXCFG register ECRETRY=0, this bit is set after 16 collisions. If TXCFG register ECRETRY=1, this bit is set after 4 Excessive Collision events (64 collisions).

#define DP83815_cmdsts_Tx_CCNT		0x000F0000 //Collision Count. If TXCFG register ECRETRY=0, this field indicates the number of collisions encountered during the transmission of this packet.
											  //If TXCFG register ECRETRY=1,CCNT[3:2] = Excessive Collisions (0-3) CCNT[1] = Multiple Collisions CCNT[0] = Single Collision
											  //Note that Excessive Collisions indicate 16 attempts failed, while multiple and single collisions indicate collisions in addition to any
											  //excessive collisions. For example a collision count of 33 includes 2 Excessive Collisions and will also set the Single Collision bit.
//tttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttttt
//Rx specific RRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRRR
#define DP83815_cmdsts_Rx_RXA		(1<<26)	//Receive Abort. Reception of this packet (frame) was aborted. Set to 1 by DP83815 when the receive was aborted, the value of this bit always equals RXO. Exists for backward compatibility.