dec21140.h

三星2410的BSP开发包

            DWORD   UnderFlowInterruptEnable : 1;   //  [5 ] 1 = enable, work together with CSR7[15] and CSR5[5]
            DWORD   ReceiveInterruptEnable : 1;     //  [6 ] 1 = enable, work together with CSR7[16] and CSR5[6]
            DWORD   RxBufferUnavailableEnable : 1;  //  [7 ] 1 = enable, work together with CSR7[15] and CSR5[7]
            DWORD   RxStoppedEnable : 1;            //  [8 ] 1 = enable, work together with CSR7[15] and CSR5[8]
            DWORD   RxWatchdogTimeoutEnable : 1;    //  [9 ] 1 = enable, work together with CSR7[15] and CSR5[9]
            DWORD   EarlyTxInterruptEnable : 1;     //  [10] 1 = enable, work together with CSR7[16] and CSR5[10]
            DWORD   GeneralPurposeTimerEnable : 1;  //  [11] 1 = enable, work together with CSR7[15] and CSR5[11]
    
            DWORD   ________Reserved__ : 1;

            DWORD   FatalBusErrorEnable : 1;        //  [13] 1 = enable, work together with CSR7[15] and CSR5[13]

            DWORD   ________Reserved___ : 1;

            DWORD   AbnormalIntrSummaryEnable : 1;  //  [15] 1 = enable
            DWORD   NormalIntrSummaryEnable : 1;    //  [16] 1 = enable     
        };

        DWORD   dwReg;
    };  

} CSR7_21140;


/////////////////////////////////////////////////////////////////////////////////
//  CSR8 === Missed frames and overflow counter
//

typedef struct tagCSR8
{
    union
    {
        struct
        {   
            DWORD   MissedFrameCounter : 16;        // [0 ] Read only... # frames discarded due to host descriptor not avail                
            DWORD   MissedFrameOverFlow : 1;        // [16] Read only... Sets when missed frame counter overflows.
                                                    //                   Reset when CSR8 is read.
            DWORD   OverflowCounter : 11;           // [17] Read only... # Frames discarded, due to overflow.   
                                                    //                   Counter cleared when read.     
            DWORD   Overflow : 1;                   // [28] Read only... Set when overflow counter overflows.
                                                    //                   Reset when CSR8 is read.
            DWORD   ________Reserved_ : 3;          
        };

        DWORD   dwReg;
    };  

} CSR8_21140;



/////////////////////////////////////////////////////////////////////////////////
//  CSR9 === Boot ROM, Serial ROM, and MII Management Register
//

typedef struct tagCSR9
{
    union
    {
        struct
        {
    
            DWORD   BootRomDataOrSerialRomCtrl : 8; //  [0 ] Data to be read / written to BootROM, if CSR9[12] is set.

            DWORD   ________Reserved_ : 2;

            DWORD   ExternalRegisterSelect : 1;     //  [10] When set 21140 selects an external register.
            DWORD   SerialRomSelect : 1;            //  [11] Select serial rom, work together with CSR9[14] or CSR9[13]
            DWORD   BootRomSelect : 1;              //  [12] 1 = select boot ROM
            DWORD   WriteOperation : 1;             //  [13] 1 = together with CSR9[12], write to boot ROM, serial ROM
                                                    //           and external register.
            DWORD   ReadOperation : 1;              //  [14] 1 = together with CSR9[12], read from boot ROM, serial ROM, 
                                                    //           and external register.

            DWORD   ________Reserved__ : 1;

            DWORD   MiiManagementClock: 1;          //  [16] 1 = mii_mdc is output signal to PHY as timing reference.
            DWORD   MiiManagementWriteData : 1;     //  [17] specifies value of data 21140 writes to PHY.
            DWORD   MiiManagementOperationMode : 1; //  [18] read or write of PHY.
            DWORD   MiiManagementDataIn : 1;        //  [19] to Read data from PHY

            DWORD   ________Reserved___ : 12;               
        };
        
        DWORD   dwReg;
    };
    
} CSR9_21140;


/////////////////////////////////////////////////////////////////////////////////
//  CSR10 === Boot ROM programming address description.
//

typedef struct tagCSR10
{
    union
    {
        struct 
        {   
            DWORD   BootRomAddress : 18 ;           //  [0 ] pointer to boot rom.
            DWORD   ________Reserved_ : 14;     
        };

        DWORD   dwReg;
    };
    
} CSR10_21140;


/////////////////////////////////////////////////////////////////////////////////
//  CSR11 === General Purpose Timer Register
//

typedef struct tagCSR11
{
    union
    {
        struct
        {   
            DWORD   TimerValue : 16;                //  [0 ] Timer value.
            DWORD   ContinuousMode: 1;              //  [16] 1 = Countinuous ; 0 = one shot.
        };

        DWORD   dwReg;
    };
    
} CSR11_21140;


/////////////////////////////////////////////////////////////////////////////////
//  CSR12 === General Purpose Port Register
//

typedef struct tagCSR12
{
    union
    {
        struct
        {
            DWORD   GPIO : 8;                       //  [0 ] 8 bit GPIO
            DWORD   GeneralPurposeControl : 1;      //  [8 ] Mode of GPIO access.
                                                    //      1 == Mode of GPIO (input or output).
                                                    //      0 == Output GPIO data to GPIO pin.
            DWORD   ________Reserved_ : 23;     
        };

        DWORD   dwReg;
    };

} CSR12_21140;


/////////////////////////////////////////////////////////////////////////////////
//  CSR15 === Watchdog Timer Register
//

#define     CSR15_MUST_AND  0xFFFFFeFF


typedef struct tagCSR15
{
    union
    {
        struct
        {
            DWORD   JabberDisable : 1;              //  [0 ] 1 = Transmit jabber function disable.
            DWORD   HostUnjab : 1;                  //  [1 ] 1 = Transmit jabber is released immediately after jabber expiration.
                                                    //       0 = Transmit jabber is released 365 ms to 420 ms after jabber exp.
            DWORD   JabberClock : 1;                //  [2 ] 1 = Tx is cut off after 2048 bytes to 2560 bytes is transmitted.
                                                    //       0 = tx for 10Mbps port is cut off after 26 ms to 33 ms.

            DWORD   ________Reserve_ : 1;

            DWORD   ReceiveWatchdogDisable : 1;     //  [4 ] 1 = disabled
                                                    //       0 = receive carriere longger than 2560 bytes are guaranteed to 
                                                    //           cause wdt counter to time out.
                                                    //           Packets shorter than 2048 bytes are guaranteed to pass.
        
            DWORD   ReceiveWatchdogRelease : 1;     //  [5 ] Time interval no carrier from receive watchdog expiration until
                                                    //       reenabling receive signal.
                                                    //       1 = 40 to 48 bit times from last carrier deassertion.
                                                    //       0 = 16 to 24 bit times from last carrier deassertion.

            DWORD   ________Reserve__ : 2;          

            DWORD   ________MUST_BE_ZERO_ : 1;      //  [8 ] !!! MUST BE ZERO !!!
        };

        DWORD   dwReg;
    };  

} 
CSR15_21140;


/* ------------------------------------------------------------------------------
 *
 *  CSR
 *
 * -------------------------------------------------------------------------------*/


typedef struct tagCSR 
{
    
    CSR0_21140      hwCSR0;     
    PAD(0,4);

    CSR_21140       hwCSR1;         //  Write only... Write with any value and 21140 checks for 
    PAD(1,4);                       //                frames to be transmitted.

    CSR_21140       hwCSR2;         //  Write only... Write with any value and 21140 checks for 
    PAD(2,4);                       //                receive descriptors to be acquired.

    CSR_21140       hwCSR3;         //  Write only... Descriptor List Address Register (Rx) 
    PAD(3,4);

    CSR_21140       hwCSR4;         //  Write only... Descriptor List Address Register (Tx)
    PAD(4,4);
    
    CSR5_21140      hwCSR5; 
    PAD(5,4);

    CSR6_21140      hwCSR6; 
    PAD(6,4);
    
    CSR7_21140      hwCSR7; 
    PAD(7,4);
    
    CSR8_21140      hwCSR8; 
    PAD(8,4);

    CSR9_21140      hwCSR9;     
    PAD(9,4);

    CSR10_21140     hwCSR10;
    PAD(a,4);
    
    CSR11_21140     hwCSR11;        
    PAD(b,4);


    CSR12_21140     hwCSR12;
    PAD(c,4);
#if 0                     //sudhakar