cache920t.s

三星2410的BSP开发包

;
; Copyright (c) 2001. Samsung Electronics, co. ltd  All rights reserved.
;
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
; -*-Text-*-
;
; $Revision: 1.5 $
;   $Author: kwelton $
;     $Date: 2000/09/27 01:12:20 $
;
; Cache920t.s - cache control routines for an ARM920T processor
;
; Copyright (c) 1998, 1999 ARM Limited
; All Rights Reserved
;

        INCLUDE armmacros.s

rPCDAT              EQU     0x15600018

        TEXTAREA

    LEAF_ENTRY OEMARMCacheMode
;++
; Routine Description:
;    Sets the C and B bits to be used to build page tables
;
; C and B bits are part of the page table entries and control write through vs.
; write back cache modes, cacheability, and write buffer use. Note that C 
; and B bit functionality is processor specific and different for the 720,
; 920, and SA1100. Consult the CPU hardware manual for the CPU
; in question before altering these bit configurations!!
; This default configuration (C=B=1)works on all current ARM CPU's and gives
: the following behaviour
; ARM720: write through, write buffer enabled
; ARM920: write back cache mode
; SA1100: write back, write buffer enabled
;
; The four valid options are:
;   ARM_NoBits      0x00000000
;   ARM_CBit        0x00000008
;   ARM_BBit        0x00000004
;   ARM_CBBits      0x0000000C
;
; Syntax:
;   DWORD OEMARMCacheMode(void);
;
; Arguments:
;   -- none --
;
; Return Value:
;  r0 must contain the desired C and B bit configuration. See description above
;  for valid bit patterns.
;
; Caution:
;  The value placed in r0 MUST be an immediate data value and NOT a predefined
;  constant. This function is called at a point in the boot cycle where the 
:  memory containing predefined constants has NOT been initialized yet.
;  --
		mov r0, #0x08
	
        RETURN

;++
; Routine Description:
;    Flush and invalidate the Instruction & Data TLBs for the ARM920
;
; Syntax:
;       void TLBClear(void);
;
; Arguments:
;       -- none --
;
; Return Value:
;       -- none --
;--
        LEAF_ENTRY TLBClear

        mcr     p15, 0, r0, c8, c5, 0           ; Invalidate I tlb
        mcr     p15, 0, r0, c8, c6, 0           ; Invalidate D tlb

        RETURN


;++
; Routine Description:
;    Flush and invalidate the Instruction Cache for ARM920
;
; Syntax:
;       void FlushICache(void);
;
; Arguments:
;       -- none --
;
; Return Value:
;       -- none --
;--
        LEAF_ENTRY      FlushICache

        mcr     p15, 0, r0, c7, c5, 0   ; flush the icache

        RETURN

;++
; Routine Description:
;    Clean and invalidate the Data Cache
;
; The following code is called to flush the dcache on the ARM920. It
; does a clean and invalidate on each cache line using the index and
; segment.
;
; Syntax:
;       void FlushDCache(void);
;
; Arguments:
;       -- none --
;
; Return Value:
;       -- none --
; r0..r1 junk
; CC flags junk
;--
        LEAF_ENTRY      FlushDCache

; r1 holds the associativity field
; r2 holds the size field
; r3 holds the line length field
; r4 is a temporary
; r5 holds the number of segments - 1
; lr holds associativity - 1

        stmfd   sp!, {r4, r5, lr}

        mrc     p15, 0, r0, c0, c0, 1   ; read the cache shape register

; extract associativity from bits 15 to 17
        mov     r1, r0, lsr #15
        and     r1, r1, #7

; extract cache size from bits 18 to 20
        mov     r2, r0, lsr #18
        and     r2, r2, #7
        add     r2, r2, #9              ; smallest size is 512 bytes

; extract line length from bits 12 and 13
        mov     r3, r0, lsr #12
        and     r3, r3, #3
        add     r3, r3, #3              ; smallest line is 8 bytes

; caclulate the number of segments
        sub     r4, r2, r1
        sub     r4, r4, r3
        mov     r5, #1
        mov     r5, r5, lsl r4
        sub     r5, r5, #1

; calculate the associativity - 1
        mov     lr, #1
        mov     lr, lr, lsl r1
        sub     lr, lr, #1

; r1 holds the shift amount for the associativity
; r2 holds the segment number
; r3 holds the shift for the segment
; r4 is a temporary

        rsb     r1, r1, #32
        mcr     p15, 0, r0, c7, c10, 4          ; drain write buffer

camloop
        mov     r0, lr, lsl r1          ; CAM index
        mov     r2, r5
blockloop
        orr     r4, r0, r2, lsl r3              ; OR in segment number
        mcr     p15, 0, r4, c7, c14, 2
        mcr     p15, 0, r0, c7, c10, 4          ; drain write buffer
        subs    r2, r2, #1
        bpl     blockloop

        subs    lr, lr, #1
        bpl     camloop

    IF Thumbing
        ldmfd   sp!, {r4, r5, lr}
        bx      lr
    ELSE
        ldmfd   sp!, {r4, r5, pc}
    ENDIF

        END

; EOF cache920t.s