📄 block_decoder.cpp
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sym ^= (val & 1); // Sign bit recovered in LSB. // Broadcast neighbourhood context changes cp[-1] |= (SIGMA_CR_BIT<<3); cp[1] |= (SIGMA_CL_BIT<<3); cword |= (SIGMA_CC_BIT<<3) | (PI_BIT<<3) | (sym<<(CHI_POS+3)); sp[width] = (sym<<31) + one_point_five; }row_2: if ((cword & (NBRHD_MASK<<6)) && !(cword & (SIG_PROP_MEMBER_MASK<<6))) { // Process third row of stripe column (row 2) state_ref = states+KAPPA_SIG_BASE+sig_lut[(cword>>6) & NBRHD_MASK]; _mq_dec_(coder,sym,*state_ref); if (!sym) { cword |= (PI_BIT<<6); goto row_3; } // Decode sign bit sym = cword & ((CHI_BIT<<3) | (SIGMA_CC_BIT<<3) | (CHI_BIT<<9) | (SIGMA_CC_BIT<<9)); sym >>= 7; // Shift down so that top sigma bit has address 0 sym |= (cp[-1] & ((CHI_BIT<<6) | (SIGMA_CC_BIT<<6))) >> (7+1); sym |= (cp[ 1] & ((CHI_BIT<<6) | (SIGMA_CC_BIT<<6))) >> (7-1); sym |= (sym >> (CHI_POS-1-SIGMA_CC_POS)); // Interleave chi & sigma val = sign_lut[sym & 0x000000FF]; state_ref = states + KAPPA_SIGN_BASE + (val>>1); _mq_dec_(coder,sym,*state_ref); sym ^= (val & 1); // Sign bit recovered in LSB. // Broadcast neighbourhood context changes cp[-1] |= (SIGMA_CR_BIT<<6); cp[1] |= (SIGMA_CL_BIT<<6); cword |= (SIGMA_CC_BIT<<6) | (PI_BIT<<6) | (sym << (CHI_POS+6)); sp[width_by2] = (sym<<31) + one_point_five; }row_3: if ((cword & (NBRHD_MASK<<9)) && !(cword & (SIG_PROP_MEMBER_MASK<<9))) { // Process fourth row of stripe column (row 3) state_ref = states+KAPPA_SIG_BASE+sig_lut[(cword>>9) & NBRHD_MASK]; _mq_dec_(coder,sym,*state_ref); if (!sym) { cword |= (PI_BIT<<9); goto done; } // Decode sign bit sym = cword & ((CHI_BIT<<6) | (SIGMA_CC_BIT<<6) | 0 | (SIGMA_CC_BIT<<12)); sym >>= 10; // Shift down so that top sigma bit has address 0 if (cword < 0) // Use the fact that NEXT_CHI_BIT = 31 sym |= CHI_BIT<<(12-10); sym |= (cp[-1] & ((CHI_BIT<<9) | (SIGMA_CC_BIT<<9))) >> (10+1); sym |= (cp[ 1] & ((CHI_BIT<<9) | (SIGMA_CC_BIT<<9))) >> (10-1); sym |= (sym >> (CHI_POS-1-SIGMA_CC_POS)); // Interleave chi & sigma val = sign_lut[sym & 0x000000FF]; state_ref = states + KAPPA_SIGN_BASE + (val>>1); _mq_dec_(coder,sym,*state_ref); sym ^= (val & 1); // Sign bit recovered in LSB. // Broadcast neighbourhood context changes cp[context_row_gap-1] |= SIGMA_TR_BIT; cp[context_row_gap ] |= SIGMA_TC_BIT | (sym<<PREV_CHI_POS); cp[context_row_gap+1] |= SIGMA_TL_BIT; cp[-1] |= (SIGMA_CR_BIT<<9); cp[1] |= (SIGMA_CL_BIT<<9); cword |= (SIGMA_CC_BIT<<9) | (PI_BIT<<9) | (sym<<(CHI_POS+9)); sp[width_by3] = (sym<<31) + one_point_five; }done: *cp = cword; } _mq_check_in_(coder);}/*****************************************************************************//* STATIC decode_mag_ref_pass_raw *//*****************************************************************************/static void decode_mag_ref_pass_raw(mq_decoder &coder, int p, bool causal, kdu_int32 *samples, kdu_int32 *contexts, int width, int num_stripes, int context_row_gap){ /* Ideally, register storage is available for 7 32-bit integers. Four 32-bit integers are declared inside the "_raw_check_out_" macro. The order of priority for these registers corresponds roughly to the order in which their declarations appear below. Unfortunately, none of these register requests are likely to be honored by the register-starved X86 family of processors, but the register declarations may prove useful to compilers for other architectures or for hand optimizations of assembly code. */ register kdu_int32 *cp = contexts; register int c; register kdu_int32 cword; _raw_check_out_(coder); // Declares t and temp as registers. register kdu_int32 *sp = samples; register kdu_int32 sym; kdu_int32 half_lsb = (1<<p)>>1; int r, width_by2=width+width, width_by3=width_by2+width; assert((context_row_gap - width) == EXTRA_DECODE_CWORDS); for (r=num_stripes; r > 0; r--, cp += EXTRA_DECODE_CWORDS, sp += width_by3) for (c=width; c > 0; c--, sp++, cp++) { if ((*cp & ((MU_BIT<<0)|(MU_BIT<<3)|(MU_BIT<<6)|(MU_BIT<<9))) == 0) { // Invoke speedup trick to skip over runs of all-0 neighbourhoods for (cp+=2; *cp == 0; cp+=2, c-=2, sp+=2); cp-=2; continue; } cword = *cp; if (cword & (MU_BIT<<0)) { // Process first row of stripe column _raw_dec_(coder,sym); sym = (1-sym)<<p; sym ^= sp[0]; sym |= half_lsb; sp[0] = sym; } if (cword & (MU_BIT<<3)) { // Process second row of stripe column _raw_dec_(coder,sym); sym = (1-sym)<<p; sym ^= sp[width]; sym |= half_lsb; sp[width] = sym; } if (cword & (MU_BIT<<6)) { // Process third row of stripe column _raw_dec_(coder,sym); sym = (1-sym)<<p; sym ^= sp[width_by2]; sym |= half_lsb; sp[width_by2] = sym; } if (cword & (MU_BIT<<9)) { // Process fourth row of stripe column _raw_dec_(coder,sym); sym = (1-sym)<<p; sym ^= sp[width_by3]; sym |= half_lsb; sp[width_by3] = sym; } } _raw_check_in_(coder);}/*****************************************************************************//* STATIC decode_mag_ref_pass *//*****************************************************************************/static void decode_mag_ref_pass(mq_decoder &coder, mqd_state states[], int p, bool causal, kdu_int32 *samples, kdu_int32 *contexts, int width, int num_stripes, int context_row_gap){ /* Ideally, register storage is available for 11 32-bit integers. Four 32-bit integers are declared inside the "_mq_check_out_" macro. The order of priority for these registers corresponds roughly to the order in which their declarations appear below. Unfortunately, none of these register requests are likely to be honored by the register-starved X86 family of processors, but the register declarations may prove useful to compilers for other architectures or for hand optimizations of assembly code. */ register kdu_int32 *cp = contexts; register int c; register kdu_int32 cword; _mq_check_out_(coder); // Declares A, C, D and t as registers. register kdu_int32 *sp = samples; register mqd_state *state_ref; register kdu_int32 sym; register kdu_int32 val; kdu_int32 half_lsb = (1<<p)>>1; int r, width_by2=width+width, width_by3=width_by2+width; states += KAPPA_MAG_BASE; assert((context_row_gap - width) == EXTRA_DECODE_CWORDS); for (r=num_stripes; r > 0; r--, cp += EXTRA_DECODE_CWORDS, sp += width_by3) for (c=width; c > 0; c--, sp++, cp++) { if ((*cp & ((MU_BIT<<0)|(MU_BIT<<3)|(MU_BIT<<6)|(MU_BIT<<9))) == 0) { // Invoke speedup trick to skip over runs of all-0 neighbourhoods for (cp+=2; *cp == 0; cp+=2, c-=2, sp+=2); cp-=2; continue; } cword = *cp; if (cword & (MU_BIT<<0)) { // Process first row of stripe column val = sp[0]; sym = (val & KDU_INT32_MAX) >> p; state_ref = states; if (sym < 4) { if (cword & (NBRHD_MASK<<0)) state_ref++; } else state_ref += 2; _mq_dec_(coder,sym,*state_ref); val ^= ((1-sym)<<p); val |= half_lsb; sp[0] = val; } if (cword & (MU_BIT<<3)) { // Process second row of stripe column val = sp[width]; sym = (val & KDU_INT32_MAX) >> p; state_ref = states; if (sym < 4) { if (cword & (NBRHD_MASK<<3)) state_ref++; } else state_ref += 2; _mq_dec_(coder,sym,*state_ref); val ^= ((1-sym)<<p); val |= half_lsb; sp[width] = val; } if (cword & (MU_BIT<<6)) { // Process third row of stripe column val = sp[width_by2]; sym = (val & KDU_INT32_MAX) >> p; state_ref = states; if (sym < 4) { if (cword & (NBRHD_MASK<<6)) state_ref++; } else state_ref += 2; _mq_dec_(coder,sym,*state_ref); val ^= ((1-sym)<<p); val |= half_lsb; sp[width_by2] = val; } if (cword & (MU_BIT<<9)) { // Process fourth row of stripe column val = sp[width_by3]; sym = (val & KDU_INT32_MAX) >> p; state_ref = states; if (sym < 4) { if (cword & (NBRHD_MASK<<9)) state_ref++; } else state_ref += 2; _mq_dec_(coder,sym,*state_ref); val ^= ((1-sym)<<p); val |= half_lsb; sp[width_by3] = val; } } _mq_check_in_(coder);}/*****************************************************************************//* STATIC decode_cleanup_pass *//*****************************************************************************/static void decode_cleanup_pass(mq_decoder &coder, mqd_state states[], int p, bool causal, int orientation, kdu_int32 *samples, kdu_int32 *contexts, int width, int num_stripes, int context_row_gap){ /* Ideally, register storage is available for 12 32-bit integers and at least the first 32-bit word of the `run_state' variable. Four 32-bit integers are declared inside the "_mq_check_out_" macro. The order of priority for these registers corresponds roughly to the order in which their declarations appear below. Unfortunately, none of these register requests are likely to be honored by the register-starved X86 family of processors, but the register declarations may prove useful to compilers for other architectures or for hand optimizations of assembly code. */ register kdu_int32 *cp = contexts; register int c; register kdu_int32 cword; _mq_check_out_(coder); // Declares A, C, D and t as registers. register mqd_state run_state = states[KAPPA_RUN_BASE]; // 64-bit register register kdu_int32 sym; register kdu_int32 val; register kdu_byte *sig_lut = significance_luts[orientation]; register kdu_int32 *sp = samples; register mqd_state *state_ref; kdu_int32 one_point_five = 1<<p; one_point_five += (one_point_five>>1); int r, width_by2=width+width, width_by3=width_by2+width; assert((context_row_gap - width) == EXTRA_DECODE_CWORDS); for (r=num_stripes; r > 0; r--, cp += EXTRA_DECODE_CWORDS, sp += width_by3) for (c=width; c > 0; c--, sp++, cp++) { if (*cp == 0) { // Enter the run mode.#ifdef USE_FAST_MACROS // Try to skip over four stripe columns at once if ((cp[3] == 0) && ((run_state.p_bar_mps & 1) == 0)) { D -= run_state.p_bar_mps<<2; if (D >= 0) { // Succeeded in skipping 4 columns at once! cp += 3; c -= 3; sp += 3; continue; } D += run_state.p_bar_mps<<2; // Put back the change. }#endif // USE_FAST_MACROS _mq_dec_(coder,sym,run_state); if (!sym) continue; _mq_dec_run_(coder,sym); // Returns run length in `sym'. cword = *cp; switch (sym) { case 0: goto row_0_significant; case 1: goto row_1_significant; case 2: goto row_2_significant; case 3: goto row_3_significant; } } cword = *cp; if (!(cword & (CLEANUP_MEMBER_MASK<<0))) { // Process first row of stripe column (row 0) state_ref = states+KAPPA_SIG_BASE+sig_lut[cword & NBRHD_MASK]; _mq_dec_(coder,sym,*state_ref); if (!sym) goto row_1;
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