if_egl.h

IXP425的BSP代码

/* if_egl.h - Interphase Eagle 4207 Ethernet driver header */

/*
modification history
--------------------
02c,22sep92,rrr  added support for c++
02b,26may92,rrr  the tree shuffle
02a,27dec91,gae  cleanup, removal of bitfields, structure simplification.
01b,04oct91,rrr  passed through the ansification filter
		  -fixed missing ;
		  -fixed #else and #endif
		  -changed TINY and UTINY to INT8 and UINT8
		  -changed copyright notice
01a,27nov90,ajm  adapted from MIPS 4.3 driver.
*/

/*
 * if_egl.h : V/Ethernet 4207 EAGLE.
 * Created  : 11/17/87 by Interphase Corp.
 * Author   : Manlio D. Marquez
 */

#ifndef __INCif_eglh
#define __INCif_eglh

#ifdef __cplusplus
extern "C" {
#endif

#define S_SHORTIO		2048	/* total short i/o space */
#define S_HUS			1812	/* total host usable space */

#define N_SCRTCH		24
#define S_SCRTCH		(sizeof(USHORT)*N_SCRTCH)

#define MAX_CQE			(S_HUS - sizeof(IOPB) - S_SCRTCH) / \
				    (sizeof (CQE) + sizeof(IOPB))

#define MAX_IOPB		MAX_CQE

#define O_MCE_IOPB		(sizeof(MCSB)+sizeof(CQE)+ \
				    (sizeof(CQE)+sizeof(IOPB))*MAX_CQE)
/* offset of MCE_IOPB */


/* Master Control Status Block (MCSB) */

/* Master Status Register
    pad:13 reserved bits
    QFC:1  Queue Flush Complete
    BOK:1  Board OK
    CNA:1  Controller Not Available
*/

#define M_MSR_QFC	0x0004
#define M_MSR_BOK	0x0002
#define M_MSR_CNA	0x0001


/* Master Control Register
    pad:2  reserved bits
    SFEN:1 Sysfail Enable
    RES:1  Reset controller
    FLQ:1  Flush Queue
    pad:8  reserved bits
    FLQR:1 Flush Queue and Report
    pad:1  reserved bits
    SQM:1  Start Queue Mode
*/

#define M_MCR_SFEN	0x2000
#define M_MCR_RES	0x1000
#define M_MCR_FLQ	0x0800
#define M_MCR_FLQR	0x0004
#define M_MCR_SQM	0x0001


/* Interrupt on Queue Available Register
    IQEA:1 Intr on Queue entry Available
    IQEH:1 Intr on Queue Half Empty Enable
    pad:3  Reserved bits
    ILVL:3 Intr Level on Queue Available
    IVCT:8 Intr Vector on Queue Available
*/

#define M_IQAR_IQEA	0x8000
#define M_IQAR_IQEH	0x4000
#define M_IQAR_ILVL	0x0700
#define M_IQAR_IVCT	0x00FF

typedef struct {		/* Master control/Status Block */
    USHORT	mcsb_MSR;	/* Master status register */
    USHORT	mcsb_RES0;	/* Reserved word 0 */
    USHORT	mcsb_MCR;	/* Master Control register */
    USHORT	mcsb_IQAR;	/* Interrupt on Queue Available Reg */
    USHORT	mcsb_QHDP;	/* Queue head pointer */
    USHORT	mcsb_RES1;	/* Reserved word 1 */
    USHORT	mcsb_RES2;	/* Reserved word 2 */
    USHORT	mcsb_RES3;	/* Reserved word 3 */
} MCSB;


/* Interface Specific Mode Physical Interface Mode
    PRM:1   Promiscuous Mode
    INL:1   Internal Loopback
    DRY:1   Disable Retry
    COL:1   Force Collision
    DTC:1   Disable Transmit CRC
    LP:1    Loopback
    DTX:1   Disable Transmit
    DRX:1   Disable Receive
    pad:4   Reserved
    PX25:1  X.25 (not supported)
    PSTR:1  Starlan (not supported)
    PIEEE:1 IEEE 802.3
    PE:1    Ethernet
*/

#define M_IMOD_PRM	0x8000
#define M_IMOD_INL	0x4000
#define M_IMOD_DRY	0x2000
#define M_IMOD_COL	0x1000
#define M_IMOD_DTC	0x0800
#define M_IMOD_LP	0x0400
#define M_IMOD_DTX	0x0200
#define M_IMOD_DRX	0x0100
#define M_IMOD_PX	0x0008
#define M_IMOD_PS	0x0004
#define M_IMOD_PIEEE	0x0002
#define M_IMOD_PE	0x0001

/* Vector structure
    pad:5	Reserved bits
    ILVL:3 Interrupt Level
    IVCT:8 Interrupt Vector
*/

#define M_VECT_ILVL	0x0700
#define M_VECT_IVCT	0x00FF

#define LVL_VCT(l,v)	((((l) << 8) & M_VECT_ILVL) | ((v) & M_VECT_IVCT))

typedef struct {		/* Controller Initialization Block */
    UINT8	cib_RES0;	/* Reserved byte 0 */
    UINT8	cib_NCQE;	/* Number of Command Queue Entries */
    USHORT 	cib_IMOD;	/* Interface Modes */
    UINT8	cib_NTXR;	/* Num LANCE Tx Rings */
    UINT8	cib_NRXR;	/* Num LANCE Rx Rings */
    UINT8	cib_PHY[6];	/* Ethernet Physical Address */
    UINT8	cib_FILT[8];	/* Ethernet Logical Address Filter */
    USHORT	cib_RXSIZ;	/* Rx Buffer Size / Length */
    USHORT	cib_NRBUF;	/* Number of Rx buffers	 */
    USHORT	cib_TXSIZ;	/* Tx Buffer Size / Length */
    USHORT	cib_NIBUF;	/* Number of Internal Tx Buffers */
    USHORT	cib_NHBUF;	/* Number of Host Managed Tx Buffers */
    USHORT	cib_NVECT;	/* Normal Completion Vector */
    USHORT	cib_EVECT;	/* Error Completion Vector */
    USHORT 	cib_BURST;	/* DMA Burst count */
    USHORT	cib_RES1[4];	/* Reserved words */
} CIB;

/* Work queue Status
    IACT:1  Initialized Active
    INACT:1 Initialized Inactive
    pad:14  Reserved Bits
*/

#define M_WQS_IACT	0x8000
#define M_WQS_INACT	0x4000

typedef struct {		/* Work Queue Information Block */
	USHORT wqib_WQS;	/* Work Queue Status */
	ULONG wqib_MAXENT;	/* Work Queue Max Entries */
	ULONG wqib_CURENT;	/* Work Queue Current Entries */
	USHORT wqib_REF;	/* Work Queue Reference Number */
	USHORT wqib_PRIO;	/* Work Queue Priority */
	USHORT wqib_WDIV;	/* Work Queue Work division */
} WQIB;

/* Command Queue Entry (CQE) */

/* Queue Entry Control Register
    pad:13 Reserved bits
    HPC:1  High Priority Command
    AA:1   Abort Acknowledge
    GO:1   Go/Busy
*/

#define M_QECR_HPC	0x0004
#define M_QECR_AA	0x0002
#define M_QECR_GO	0x0001

typedef struct {		/* Command Queue Entry */
    USHORT cqe_QECR;		/* Queue Entry Control Register */
    USHORT cqe_IOPB_ADDR;	/* IOPB Address */
    ULONG cqe_CTAG;		/* Command Tag */
    UINT8 cqe_RES0;		/* Reserved */
    UINT8 cqe_WORK_QUEUE;	/* Work Queue Number */
    USHORT cqe_RES1;		/* Reserved word */
} CQE;

/* Command Response Block (CRB) */

/* CRSW Command Response Status Word
    pad:9  Reserved bits
    QEA:1  Queue Entry Available
    QMS:1  Queue Mode Started
    AQ:1   Abort Queue
    EX:1   Exception
    ER:1   Error
    CC:1   Command Complete
    CRBV:1 Command Response Block Valid/Clear
*/

#define M_CRSW_QEA	0x0040
#define M_CRSW_QMS	0x0020
#define M_CRSW_AQ	0x0010
#define M_CRSW_EX	0x0008
#define M_CRSW_ER	0x0004
#define M_CRSW_CC	0x0002
#define M_CRSW_CRBV	0x0001


typedef struct {		/* Command Response Block */
    USHORT crb_CRSW;		/* Command Response Status Word */
    USHORT crb_RES0;		/* Reserved word */
    ULONG crb_CTAG;		/* Command Tag */
    UINT8 crb_RES1;		/* Reserved byte */
    UINT8 crb_WORK_QUEUE;	/* Work Queue Number */
    USHORT crb_RES2;		/* Reserved word */
} CRB;


/* Configuration Status Block (CSTB) */

typedef struct {		/* Configuration Status Block 72 bytes */
    UINT8 cstb_RES0;		/* Reserved byte */
    UINT8 cstb_PCODE[3];	/* Product Code */
    UINT8 cstb_RES1;		/* Reserved byte */
    UINT8 cstb_PVAR;		/* Product Variation */
    UINT8 cstb_RES2;		/* Reserved byte */
    UINT8 cstb_FREV[3];		/* Firmware Revision level */