if_dcfast.c

IXP425的BSP代码

 /* if_dcFast.c - DEC 21040 PCI Ethernet LAN network interface driver */

/* Copyright 1984-1995 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01e,06mar96,rcp  added support for the DEC21140 100Mbit Controller
01d,05sep95,vin  added filter Frame setup, added PROMISCOUS MODE to ioctl,
		 changed all ln references to dc, added flag DC_MULTICAST_FLAG.
01c,05apr95,vin  added AUI/10BASE-T dynamic configuration support. 
01b,31mar95,caf  changed name from "dcPci" to "dc".
01a,03mar95,vin	 written.
*/

/* FROM ROB PERSONS - Motorola Computer Group (March 06, 1996)
The comments below describe the primary operation and configuration of
the DEC 21X40 driver.  Differences between the two DEC parts will be 
outlined in this section and how the original driver was modified to
accomodate the differences.

The DEC21140 is very similar to the original DEC21040 but it also has the
ability to operate on networks at 100-Mb/s along with 10-Mb/s.  The
physical interface is no longer part of the chip so configuration of
the CSR registers which control the AUI and TP interfaces is no longer
applicable.  This part now provides 100-Mb/s MII/SYM 10-Mb/s Serial
intefaces which are then converted to the appropriate external interface
with some additional hardware.  Most of the driver will be uneffected
by the new part.  

In the early stages of the driver initialization, the driver will
use the Configuration ID Register (CFID) to determine which of the
two parts is to be used.  A global flag will indicate which device
is in use and its state will be used along with the driver modifications
to accomodate the DEC21140. 

The Status Register (CSR5) has three bits which have different behavior.
Bit 12 (Link Fail Status) and Bit 10 (AUI/TP Status) are no longer used
by the DEC21140.  Bit 11 in the DEC21040 indicates a Full-Duplex Short
Frame was Received which in the DEC21140 it indicates the General Purpose
Timer(GPT)  has expired.  The GPT is a new feature with the DEC21140.  Bit 
11 is currently not used in the drive and there are no plans on adding support 
for the GPT so at this time it will be ignored.

The Operating Mode Register (CSR6) is significantly different.  Many of the
bits reflect the difference in the MII/SYM interface for the 100-Mb/s 
interface.  To make the driver as flexible as possible, logic will be added 
to the dcattach function to allow for the configuration of all these 
control bits at driver configuration.  The following modes will be added:

DEC21140 Flag	- This flag indicates the driver will be operating with
		  a DEC21140 chip and not the DEC21040.
100Mb/s Mode	- This flag will be used to set a bits in the CSR6 for the
		  DEC21140.  The Transmit Threshold Mode and Heartbeat Disable
		  bits will be effect.
Scramble Mode 	- The scrambler function is active and the MII/SYM port 
	          transmits and received scrambled symbols.
PCS Function	- The PCS functions are active and MII/SYM port operates
		  in symbol mode.  All MII/SYM port cont andol signals are 
		  generated internally bits will be effect.
Port Select	- When selected the MII/SYM mode is active.  All 100-Mb/s
		  modes require this.
Full Duplex Mode- When selected the Lance Chip Operates in Full Duplex Mode.
		  It is important that the can operate in Full Duplex mode
		  as well. 
Int Loopback    - An additional mode was added for doing internal loopback.
Ext Loopback    - An additional mode was added for doing external loopback.
HB Enable	- An additional mode was added for testing, enableing heartb.

If none of these mode bits are selected, the DEC21140 will default to the
MII interface with transmit FIFO thresholds appropriate for 10-Mb/s.

Additional code will be added to deal with the different Serial ROM interface.
The DEC21140 now has a new interface to access a R/W ROM part to store ethernet
addresses.  The dcEnetAddrGet will be modified to add the proper logic to
read the DEC21140 Serial ROM interface.  No logic will be added to reprogram
the value.  It turns out the DEC PMC 520-AA only stores the last 2 bytes of the
ethernet address in the ROM.  The driver will make the assumption that the
VENDOR ID portion extends to from 0-3 where bytes 0-2 are the manufacturers
assigned values and byte 3 is assigned by DEC for the class of products.

The remaining Host to Controller interface is identical and should not be 
effected by the new part.

*/



/*
This module implements the DEC 21040-PCI Ethernet 32 bit network interface
driver.

The DEC 21040-PCI ethernet controller is inherently little endian because
the chip is designed to operate on a PCI bus which is a little endian
bus. The software interface to the driver is divided into three parts.
The first part is the PCI configuration registers and their set up. 
This part is done at the BSP level in the various BSPs which use this
driver. The second and third part are dealt in the driver. The second
part of the interface comprises of the I/O control registers and their
programming. The third part of the interface comprises of the descriptors
and the buffers. 

This driver is designed to be moderately generic, operating unmodified
across the range of architectures and targets supported by VxWorks.  To
achieve this, the driver must be given several target-specific parameters,
and some external support routines must be provided.  These parameters,
and the mechanisms used to communicate them to the driver, are detailed
below.  If any of the assumptions stated below are not true for your
particular hardware, this driver will probably not function correctly with
it.

This driver supports upto 4 lance units per CPU.  The driver can be
configured to support big-endian or little-endian architectures.  It
contains error recovery code to handle known device errata related to DMA
activity.

This driver configures the 10BASE-T interface by default and waits for
two seconds to check the status of the link. If the link status is fail
then it configures the AUI interface. 

Big endian processors can be connected to the PCI bus through some controllers
which take care of hardware byte swapping. In such cases all the registers 
which the chip DMA s to have to be swapped and written to, so that when the
hardware swaps the accesses, the chip would see them correctly. The chip still
has to be programmed to operated in little endian mode as it is on the PCI bus.
If the cpu board hardware automatically swaps all the accesses to and from the
PCI bus, then input and output byte stream need not be swapped. 

BOARD LAYOUT
This device is on-board.  No jumpering diagram is necessary.

EXTERNAL INTERFACE
This driver provides the standard external interface with the following
exceptions.  All initialization is performed within the attach routine;
there is no separate initialization routine.  Therefore, in the global interface
structure, the function pointer to the initialization routine is NULL.

The only user-callable routine is dcattach(), which publishes the `dc'
interface and initializes the driver and device.

TARGET-SPECIFIC PARAMETERS
.iP "bus mode"
This parameter is a global variable that can be modified at run-time.

The LAN control register #0 determines the bus mode of the device,
allowing the support of big-endian and little-endian architectures.
This parameter, defined as "ULONG dcCSR0Bmr", is the value that will
be placed into LANCE control register #0. The default is mode is little
Endian.
For information about changing this parameter, see the manual
.I "DEC  Local Area Network Controller DEC21040 or DEC21140 for PCI."

.iP "base address of device registers"
This parameter is passed to the driver by dcattach().

.iP "interrupt vector"
This parameter is passed to the driver by dcattach().

This driver configures the LANCE device to generate hardware interrupts
for various events within the device; thus it contains
an interrupt handler routine.  The driver calls intConnect() to connect 
its interrupt handler to the interrupt vector generated as a result of 
the LANCE interrupt.

.iP "interrupt level"
This parameter is passed to the driver by dcattach().

Some targets use additional interrupt controller devices to help organize
and service the various interrupt sources.  This driver avoids all
board-specific knowledge of such devices.  During the driver's
initialization, the external routine sysLanIntEnable() is called to
perform any board-specific operations required to allow the servicing of a
LANCE interrupt.  For a description of sysLanIntEnable(), see "External
Support Requirements" below.

This parameter is passed to the external routine.

.iP "shared memory address"
This parameter is passed to the driver by dcattach().

The LANCE device is a DMA type of device and typically shares access to
some region of memory with the CPU.  This driver is designed for systems
that directly share memory between the CPU and the LANCE.  It
assumes that this shared memory is directly available to it
without any arbitration or timing concerns.

This parameter can be used to specify an explicit memory region for use
by the LANCE.  This should be done on hardware that restricts the LANCE
to a particular memory region.  The constant NONE can be used to indicate
that there are no memory limitations, in which case, the driver 
attempts to allocate the shared memory from the system space.

.iP "shared memory size"
This parameter is passed to the driver by dcattach().

This parameter can be used to explicitly limit the amount of shared
memory (bytes) this driver will use.  The constant NONE can be used to
indicate no specific size limitation.  This parameter is used only if
a specific memory region is provided to the driver.

.iP "shared memory width"
This parameter is passed to the driver by dcattach().

Some target hardware that restricts the shared memory region to a
specific location also restricts the access width to this region by
the CPU.  On these targets, performing an access of an invalid width
will cause a bus error.

This parameter can be used to specify the number of bytes of access
width to be used by the driver during access to the shared memory.
The constant NONE can be used to indicate no restrictions.

Current internal support for this mechanism is not robust; implementation 
may not work on all targets requiring these restrictions.

.iP "shared memory buffer size"
This parameter is passed to the driver by dcattach().

The driver and LANCE device exchange network data in buffers.  This
parameter permits the size of these individual buffers to be limited.
A value of zero indicates that the default buffer size should be used.
The default buffer size is large enough to hold a maximum-size Ethernet
packet.

.iP "pci Memory base"
This parameter is passed to the driver by dcattach(). This parameter
gives the base address of the main memory on the PCI bus. 

.iP "dcOpMode"
This parameter is passed to the driver by dcattach(). This parameter
gives the mode of initialization of the device. The mode flags for both
the DEC21040 and DEC21140 interfaces are listed below.  

DC_PROMISCUOUS_FLAG     0x01 
DC_MULTICAST_FLAG	0x02

The mode flags specific to the DEC21140 interface are listed below.

DC_100_MB_FLAG          0X04
DC_21140_FLAG           0x08
DC_SCRAMBLER_FLAG       0X10
DC_PCS_FLAG             0x20
DC_PS_FLAG              0x40

The Full Duplex Mode was added to the driver.
DC_FULLDUPLEX_FLAG      0x80

Loopback mode flags
DC_ILOOPB_FLAG          0x100 
DC_ELOOPB_FLAG          0x200
DC_HBE_FLAG	        0x400


.iP "Ethernet address"
This is obtained by the driver by reading an ethernet ROM register 
interfaced with the device.

.LP

EXTERNAL SUPPORT REQUIREMENTS
This driver requires one external support function:
.iP "void sysLanIntEnable (int level)" "" 9 -1
This routine provides a target-specific enable of the interrupt for
the LANCE device.  Typically, this involves interrupt controller hardware,
either internal or external to the CPU.

This routine is called once, from the dcattach() routine.
.LP

SEE ALSO: ifLib, 
.I "DECchip 21040 or 21140 Ethernet LAN Controller for PCI."
*/

#include "vxWorks.h"
#include "stdlib.h"
#include "taskLib.h"
#include "logLib.h"
#include "intLib.h"
#include "netLib.h"
#include "stdio.h"
#include "stdlib.h"
#include "sysLib.h"
#include "iv.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sys/ioctl.h"
#include "etherLib.h"

#ifndef DOC             /* don't include when building documentation */
#include "net/mbuf.h"
#endif  /* DOC */

#include "net/protosw.h"
#include "sys/socket.h"
#include "errno.h"

#include "net/if.h"
#include "net/route.h"

#include "netinet/in.h"
#include "netinet/in_systm.h"
#include "netinet/in_var.h"
#include "netinet/ip.h"
#include "netinet/if_ether.h"
#include "net/if_subr.h"
#include "semLib.h"

#include "drv/netif/if_dcFast.h"	/* device description header */

/* defines */

#define DC_BUFSIZ      (ETHERMTU + SIZEOF_ETHERHEADER + 6)
#define MAX_UNITS       4	/* maximum units supported */
#define DC_L_POOL	0x10	/* number of Rx loaner buffers in pool */
#define LOOP_PER_NS 4
#define DELAY(count)	{\
			volatile int cx = 0;\
			for (cx = 0; cx < (count); cx++);\
			}
#define NSDELAY(nsec)	{\
			volatile int nx = 0;\
			volatile int loop = (int)(nsec*LOOP_PER_NS);\
			for (nx = 0; nx < loop; nx++);\
			}
/* RCP: Added DEC Part Check */
#define DEC21140(x)	 ((x & DC_21140_FLAG) && (x != NONE)) 
/*
 * If DC_KICKSTART_TX is TRUE the transmitter is kick-started to force a
 * read of the transmit descriptors, otherwise the internal polling (1.6msec)
 * will initiate a read of the descriptors.  This should be FALSE is there
 * is any chance of memory latency or chip accesses detaining the LANCE DMA,
 * which results in a transmitter UFLO error.  This can be changed with the
 * global dcKickStartTx below.
 */

#define DC_KICKSTART_TX TRUE

/* Cache macros */

#define DC_CACHE_INVALIDATE(address, len) \
        CACHE_DRV_INVALIDATE (&pDrvCtrl->cacheFuncs, (address), (len))

#define DC_CACHE_VIRT_TO_PHYS(address) \
        CACHE_DRV_VIRT_TO_PHYS (&pDrvCtrl->cacheFuncs, (address))

#define DC_CACHE_PHYS_TO_VIRT(address) \
        CACHE_DRV_PHYS_TO_VIRT (&pDrvCtrl->cacheFuncs, (address))

/* memory to PCI address translation macros */

#define PCI_TO_MEM_PHYS(pciAdrs) \
	((pciAdrs) - (pDrvCtrl->pciMemBase))
	
#define MEM_TO_PCI_PHYS(memAdrs) \
	((memAdrs) + (pDrvCtrl->pciMemBase))

/* Typedefs for external structures that are not typedef'd in their .h files */

typedef struct mbuf MBUF;
typedef struct arpcom IDR;                  /* Interface Data Record wrapper */
typedef struct ifnet IFNET;                 /* real Interface Data Record */
typedef struct sockaddr SOCK;

/* The definition of the driver control structure */

typedef struct drv_ctrl
    {
    IDR		idr;			/* Interface Data Record */
    int		dcNumRds;		/* RMD ring size */
    int		rxIndex;                /* index into RMD ring */
    DC_RDE *	rxRing;			/* RMD ring */
    int		dcNumTds;		/* TMD ring size */
    int		txIndex;		/* index into TMD ring */
    int		txDiIndex;		/* disposal index into TMD ring */
    DC_TDE *	txRing;			/* TMD ring */
    BOOL        attached;               /* indicates unit is attached */
    SEM_ID      TxSem;                  /* transmitter semaphore */
    ULONG	dcOpMode;		/* mode of operation */
    int         ivec;                   /* interrupt vector */
    int         ilevel;                 /* interrupt level */
    ULONG	devAdrs;                /* device structure address */
    ULONG	pciMemBase;		/* memory base as seen from PCI*/
    int         memWidth;               /* width of data port */
    CACHE_FUNCS cacheFuncs;             /* cache function pointers */
    int		nLoanRx;		/* number of Rx buffers left to loan */
    char	*lPool[DC_L_POOL];	/* receive loaner pool ptrs */
    UINT8	*pRefCnt[DC_L_POOL];	/* stack of reference count pointers */
    UINT8	refCnt[DC_L_POOL];	/* actual reference count values */
    ULONG *	pFltrFrm;		/* pointer to setup filter frame */
    } DRV_CTRL;

#define DRV_CTRL_SIZ		sizeof(DRV_CTRL)
#define RMD_SIZ			sizeof(DC_RDE)
#define TMD_SIZ			sizeof(DC_TDE)

/* globals */

/*  RCP: Reference Removed for new function
IMPORT void sysLanIntEnable ();
*/
IMPORT BOOL arpresolve ();
/*
IMPORT unsigned char dcEnetAddr []; *//* Ethernet address to load into lance */


BOOL 	dcKickStartTx 	= DC_KICKSTART_TX;