if_lnisa_eeprom.c

IXP425的BSP代码

  EE_TIMEOUT;
  EE_TIMEOUT;
  WR_EE_REG(RD_EE_REG | EE_CS);   /* select Chip Select to determine write OK*/

  taskDelay(EE_TWP);
  if(RD_EE_REG & EE_DATA)
    stat = OK;
  else
  {
#ifdef LNISA_DEBUG
    printf("EEPROM Write Failed\n");
#endif
    stat = ERROR;
  }

  WR_EE_REG(RD_EE_REG & (~EE_CS));   /* clear Chip Select */
  return stat;
}

/* 
 * lnIsa_eeread16 - read 16 data bits from the word at wordAddr in the device.
 *
 * wordAddr is in the range of 0 - 128 for a 93C56 device.
 * 
 * NOTES:
 *  Since the data was written in bit reversal format, it has to be read 
 *  back in the same fashion. So Bit 0 is read first instead of Bit 15.
 */
UINT16 lnIsa_eeread16(DRV_CTRL *pDrvCtrl,UINT8 wordAddr)
{
  int i;
  UINT8 addrMask = 0x80;
  UINT16 dataMask = 0x0001; /* was 0x8000 */
  UINT16 dataRead = 0;

  WR_EE_REG(RD_EE_REG | EE_CS);   /* assert Chip Select */
  EE_TIMEOUT;

  lnIsa_eewriteBit(pDrvCtrl,1); /* send start bit */
  lnIsa_eewriteBit(pDrvCtrl,1); /* send first command bit */
  lnIsa_eewriteBit(pDrvCtrl,0); /* send second command bit */

  /* Send the Address */
  for(i = 0; i < 8; i++)
  {
    lnIsa_eewriteBit(pDrvCtrl, (int)(addrMask & wordAddr));
    addrMask = addrMask >> 1; 
  }
  
  /* read the data */
  for(i = 0; i < 16; i++)
  {
    if(lnIsa_eereadBit(pDrvCtrl))
      dataRead |= dataMask;
    dataMask = dataMask << 1; /* was >> */
  }

  /* clear CS to finish read sequence */
  WR_EE_REG(RD_EE_REG & (~EE_CS));   /* clear Chip Select */
  EE_TIMEOUT;
  EE_TIMEOUT;

  return dataRead;

}


/*
 * lnIsa_eewen - send Write Enable Command to EEPROM
 */
void lnIsa_eewen(DRV_CTRL *pDrvCtrl)
{
  int wen[] = { 1,0,0,1,1,0,0,0,0,0,0 };
  int i;

  WR_EE_REG(RD_EE_REG | EE_CS);   /* assert Chip Select */
  EE_TIMEOUT;
  for(i = 0; i < 11; i++)
    lnIsa_eewriteBit(pDrvCtrl,wen[i]);

  WR_EE_REG(RD_EE_REG & (~EE_CS));   /* clear Chip Select */
  EE_TIMEOUT;

}

/*
 * lnIsa_eewds - send Write Disable Command to EEPROM
 */
void lnIsa_eewds(DRV_CTRL *pDrvCtrl)
{
  int wds[] = { 1,0,0,0,0,0,0,0,0,0,0 };
  int i;

  WR_EE_REG(RD_EE_REG | EE_CS);   /* assert Chip Select */
  EE_TIMEOUT;
  for(i = 0; i < 11; i++)
    lnIsa_eewriteBit(pDrvCtrl,wds[i]);

  WR_EE_REG(RD_EE_REG & (~EE_CS));   /* clear Chip Select */
  EE_TIMEOUT;

}

/*
 * lnIsa_eeeraseall - erase the entire device
 */
void lnIsa_eeeraseall(DRV_CTRL *pDrvCtrl)
{
  int eral[] = { 1,0,0,1,0,0,0,0,0,0,0 };
  int i;

  lnCsrWrite(pDrvCtrl,0,4); /* place the device in the STOP state */

  WR_EE_REG(EE_EN);	/* enable the EEPROM interface */
  EE_TIMEOUT;

  lnIsa_eewen(pDrvCtrl); /* enable write access to EEPROM */

  WR_EE_REG(RD_EE_REG | EE_CS);   /* assert Chip Select */
  EE_TIMEOUT;

  for(i = 0; i < 11; i++)
    lnIsa_eewriteBit(pDrvCtrl,eral[i]);

  WR_EE_REG(RD_EE_REG & (~EE_CS));   /* clear Chip Select */
  EE_TIMEOUT;
  EE_TIMEOUT;
  WR_EE_REG(RD_EE_REG | EE_CS);   /* select Chip Select to determine erase OK*/

  taskDelay(EE_TWP);
#ifdef LNISA_DEBUG
  if(!(RD_EE_REG & EE_DATA))
    printf("EEPROM Erase Failed\n");
#endif

  WR_EE_REG(RD_EE_REG & (~EE_CS));   /* clear Chip Select */
  lnIsa_eewds(pDrvCtrl);	/* disable writes to EEPROM */
  WR_EE_REG(0); /* Disable EEPROM access */
}

/*
 * lnIsa_eewriteBit - write a single bit to the EEPROM. 
 * 
 * PARAMS:
 * 	bit - if zero write a zero, if non-zero write a one.
 */	
void lnIsa_eewriteBit(DRV_CTRL *pDrvCtrl, int bit)
{
  UINT16 eeData;
  UINT16 eeReg;
  /* 
   * All bits are clocked into chip on a lo to hi transition of SK, so 
   * set it lo to start.
   */
  if(bit)
    eeData = EE_DATA;
  else
    eeData = 0;

  /* 
   * Read current contents of EE register.
   * Clear out the DATA bit, so a simple OR will suffice later when setting
   * up the bit to write. Set the clock low, as data is clocked in on the
   * rising edge of clock.
   */
  eeReg = RD_EE_REG;
  eeReg &= (~(EE_SK | EE_DATA)); 
  WR_EE_REG(eeReg); /* set clock low */
  EE_TIMEOUT;

  eeReg |= eeData;
  WR_EE_REG(eeReg);	/* set up the data */
  EE_TIMEOUT;
  eeReg |= EE_SK;
  WR_EE_REG(eeReg); /* clock the bit into the EEPROM */
  EE_TIMEOUT;

}
			   
/*
 * lnIsa_eereadBit - clock in a bit from the EEPROM
 */
int lnIsa_eereadBit(DRV_CTRL *pDrvCtrl)
{
  UINT16 retBit = 0;
  UINT16 eeReg;

  eeReg = RD_EE_REG;
  eeReg &= ~(EE_SK); 
  WR_EE_REG(eeReg); /* set clock low */
  EE_TIMEOUT;
  eeReg |= EE_SK;   
  WR_EE_REG(eeReg); /* set clock High */
  EE_TIMEOUT;
  retBit = RD_EE_REG & EE_DATA;
  EE_TIMEOUT;

  return (int)retBit;
}

/* 
 * lnIsa_eetimeout - Since a sysInWord takes at least 130 nSec then use 
 *		an lnIdpRead to generate the required timeout for the EEPROM 
 * 		Shift Clock. There are two reads per lnIdpRead so each == 260 
 *		nSecs. The 93C56 max clock rate is 1 Mhz. We should be well 
 *              within this using this method.
 */

void lnIsa_eetimeout(DRV_CTRL *pDrvCtrl)
{
  int i;
  for(i = 0; i < 10; i++)
    RD_EE_REG;
}

/*
 * pnpInitiation - write the Plug 'n Play initiation sequence to the PnP 
 * 		   address port. This prepares all PnP devices for the 
 * 		   isolation algorithm
 *
 * Note: The sequence must be written monolithically. Any other accesses to 
 * the PNP_ADDR_PORT must be disabled while the init sequence is being 
 * written. This may include disabling interrupts.
 *
 */
UINT8 pnpInitKey [] = { 0x6a, 0xb5, 0xda, 0xed, 0xf6, 0xfb, 0x7d, 0xbe,
			 0xdf, 0x6f, 0x37, 0x1b, 0x0d, 0x86, 0xc3, 0x61,
			 0xb0, 0x58, 0x2c, 0x16, 0x8b, 0x45, 0xa2, 0xd1,
			 0xe8, 0x74, 0x3a, 0x9d, 0xce, 0xe7, 0x73, 0x39 };


UINT8 pnpRelocateKey [] = { 0x6b, 0x35, 0x9a, 0xcd, 0xe6, 0xf3, 0x79, 0xbc,
			    0x5e, 0xaf, 0x57, 0x2b, 0x15, 0x8a, 0xc5, 0xe2,
			    0xf1, 0xf8, 0x7c, 0x3e, 0x9f, 0x4f, 0x27, 0x13,
			    0x09, 0x84, 0x42, 0xa1, 0xd0, 0x68, 0x34, 0x1a };

/*
 * lnIsaPnPInitiation - send the PnP software relocatable Key to the AMD961
 *			to take it out of "Wait for Key" state. These writes
 *			must occur sequencially, any extraneous writes to the 
 *			PNP_ADDR_PORT will cause the initiation to fail.
 */
void lnIsaPnPInitiation(void)
{
  int i;

  sysOutByte (PNP_ADDR_PORT,PNP_CONFIG_CTRL);
  sysOutByte (PNP_WR_PORT,2);	/* Set Wait for Key State */

  /* send Initiation Key */
  sysOutByte(PNP_ADDR_PORT, 0);	/* reset comparison logic */
  sysOutByte(PNP_ADDR_PORT, 0);
  for(i = 0; i < PNP_INIT_KEY_LEN; i++)
    sysOutByte(PNP_ADDR_PORT, pnpRelocateKey[i]); /* write initiation key */

}

/*
 * lnIsaPnPSetup - set up the necessary Plug n' Play registers
 * 		   and activate the device on the ISA bus. This function
 *		   allows the AMD961 to be placed in a mode such that the
 * 		   the EEPROM may be programmed with the Plug n' Play 
 *		   information.
 */
void lnIsaPnPSetup (char * ioAdrs, UINT8 intLvl, UINT8 intType,
		    UINT8 dmaChan)
{
  sysOutByte (PNP_ADDR_PORT,PNP_WAKE);
  sysOutByte (PNP_WR_PORT,0);	/* write 0 to WAKE to enter Isolation */

  sysOutByte (PNP_ADDR_PORT,PNP_SET_RD_DATA);
  sysOutByte (PNP_WR_PORT,(PNP_RD_PORT >> 2)); /* Init READ-PORT */

  sysOutByte (PNP_ADDR_PORT,PNP_CSN);
  sysOutByte (PNP_WR_PORT,4);	/* Set up non-zero CSN */

  sysOutByte (PNP_ADDR_PORT,PNP_WAKE);
  sysOutByte (PNP_WR_PORT,4);	/* write CSN of 4 (arbitrary) to WAKE to 
				   enter Config Mode */

  sysOutByte (PNP_ADDR_PORT,PNP_DEV_NUM);

  /* set the IO address range */
  sysOutByte(PNP_ADDR_PORT,PNP_IO_BASE0_HIBYTE);
  sysOutByte(PNP_WR_PORT,(UINT8)((UINT32)(ioAdrs)>>8));

  sysOutByte(PNP_ADDR_PORT,PNP_IO_BASE0_LOBYTE);
  sysOutByte(PNP_WR_PORT,(UINT8)((UINT32)ioAdrs & 0xff));

  /* set up the Interrupt level and type */
  sysOutByte(PNP_ADDR_PORT,PNP_IRQ_LEVEL_SEL0);
  sysOutByte(PNP_WR_PORT,intLvl);

  sysOutByte(PNP_ADDR_PORT,PNP_IRQ_TYPE_SEL0);
  sysOutByte(PNP_WR_PORT,intType);

  /* set the DMA Channel */
  sysOutByte(PNP_ADDR_PORT,PNP_DMA_CHANNEL_SEL0);
  sysOutByte(PNP_WR_PORT,dmaChan);

  /* enable the device on the ISA bus */
  sysOutByte(PNP_ADDR_PORT,PNP_IO_RANGE);
  sysOutByte(PNP_WR_PORT,0x0); /* disable IO range check */
  sysOutByte(PNP_ADDR_PORT,PNP_ACTIVATE);
  sysOutByte(PNP_WR_PORT,0x01); /* Put us on the ISA bus */

  /* take device out of Config mode */
  sysOutByte(PNP_ADDR_PORT,PNP_CONFIG_CTRL);
  sysOutByte(PNP_WR_PORT,PNP_CONFIG_CTRL_WAITFORKEY); /*back to Wait for Key */
    
}

#ifdef LNISA_DEBUG
/* 
 * idpWrite - local version of lnIdpWrite
 */
void idpWrite
    (
    int 	reg,			/* register to select */
    UINT16 	value			/* value to write */
    )
    {
    int dv = (int)IO_ADRS_LNISA;

    /* select IDP */
    sysOutWord(dv+0x12,reg);;

    /* write val to IDP */
    sysOutWord(dv+0x16,value);;

    }

UINT16 idpRead
    (
    int		reg			/* register to select */
    )
    {
    int dv = (int)IO_ADRS_LNISA;

    /* select IDP register */
    sysOutWord(dv+0x12,reg);;

    /* get contents of IDP register */
    return (sysInWord(dv+0x16));

    }

void csrWrite
    (
    int 	reg,			/* register to select */
    USHORT 	value			/* value to write */
    )
    {
    int dv = (int)IO_ADRS_LNISA;

    /* select CSR */
    sysOutWord(dv+0x12,reg);;

    /* write val to CSR */
    sysOutWord(dv+0x10,value);;

    }

UINT16 csrRead
    (
    int		reg			/* register to select */
    )
    {
    int dv = (int)IO_ADRS_LNISA;

    /* select CSR */
    sysOutWord(dv+0x12,reg);;

    /* get contents of CSR */
    return (sysInWord(dv+0x10));

    }
#endif /* LNISA_DEBUG */