motcpmend.h

IXP425的BSP代码

#define SCC_ETHER_RX_BD_W       0x2000          /* last BD in ring */
#define SCC_ETHER_RX_BD_E       0x8000          /* buffer is empty */
 
/* SCC Ethernet Transmit Buffer Descriptor definitions */
 
#define SCC_ETHER_TX_BD_CSL     0x0001          /* carrier sense lost */
#define SCC_ETHER_TX_BD_UN      0x0002          /* underrun */
#define SCC_ETHER_TX_BD_RC      0x003c          /* retry count */
#define SCC_ETHER_TX_BD_RL      0x0040          /* retransmission limit */
#define SCC_ETHER_TX_BD_LC      0x0080          /* late collision */
#define SCC_ETHER_TX_BD_HB      0x0100          /* heartbeat */
#define SCC_ETHER_TX_BD_DEF     0x0200          /* defer indication */
#define SCC_ETHER_TX_BD_TC      0x0400          /* auto transmit CRC */
#define SCC_ETHER_TX_BD_L       0x0800          /* buffer is last in frame */
#define SCC_ETHER_TX_BD_I       0x1000          /* interrupt on transmit */
#define SCC_ETHER_TX_BD_W       0x2000          /* last BD in ring */
#define SCC_ETHER_TX_BD_PAD     0x4000          /* auto pad short frames */
#define SCC_ETHER_TX_BD_R       0x8000          /* buffer is ready */

/* typedefs */

/* SCC - Serial Comunications Controller */

typedef struct          /* SCC_ETHER_PROTO */
    {
    UINT32      	c_pres;             /* preset CRC */
    UINT32      	c_mask;             /* constant mask for CRC */
    volatile UINT32     crcec;              /* CRC error counter */
    volatile UINT32     alec;               /* alignment error counter */
    volatile UINT32     disfc;              /* discard frame counter */
    UINT16      	pads;               /* short frame pad value */
    UINT16      	ret_lim;            /* retry limit threshold */
    volatile UINT16     ret_cnt;            /* retry limit counter */
    UINT16      	mflr;               /* maximum frame length register */
    UINT16      	minflr;             /* minimum frame length register */
    UINT16      	maxd1;              /* max DMA1 length register */
    UINT16      	maxd2;              /* max DMA2 length register */
    volatile UINT16     maxd;               /* Rx max DMA */
    volatile UINT16     dma_cnt;            /* Rx DMA counter */
    volatile UINT16     max_b;              /* max BD byte count */
    UINT16      	gaddr1;             /* group address filter 1 */
    UINT16      	gaddr2;             /* group address filter 2 */
    UINT16      	gaddr3;             /* group address filter 3 */
    UINT16      	gaddr4;             /* group address filter 4 */
    volatile UINT32     tbuf0_data0;        /* save area 0 - current frame */
    volatile UINT32     tbuf0_data1;        /* save area 1 - current frame */
    volatile UINT32     tbuf0_rba0;         /* ? */
    volatile UINT32     tbuf0_crc;          /* ? */
    volatile UINT16     tbuf0_bcnt;         /* ? */
    UINT16      	paddr1_h;           /* physical address 1 (MSB) */
    UINT16      	paddr1_m;           /* physical address 1 */
    UINT16      	paddr1_l;           /* physical address 1 (LSB) */
    UINT16      	p_per;              /* persistence */
    volatile UINT16     rfbd_ptr;           /* Rx first BD pointer */
    volatile UINT16     tfbd_ptr;           /* Tx first BD pointer */
    volatile UINT16     tlbd_ptr;           /* Tx last BD pointer */
    volatile UINT32     tbuf1_data0;        /* save area 0 - next frame */
    volatile UINT32     tbuf1_data1;        /* ? */
    volatile UINT32     tbuf1_rba0;         /* ? */
    volatile UINT32     tbuf1_crc;          /* ? */
    volatile UINT16     tbuf1_bcnt;         /* ? */
    volatile UINT16     tx_len;             /* Tx frame length counter */
    UINT16      	iaddr1;             /* individual address filter 1 */
    UINT16      	iaddr2;             /* individual address filter 2 */
    UINT16      	iaddr3;             /* individual address filter 3 */
    UINT16      	iaddr4;             /* individual address filter 4 */
    volatile UINT16     boff_cnt;           /* backoff counter */
    UINT16      	taddr_h;            /* temp address (MSB) */
    UINT16      	taddr_m;            /* temp address */
    UINT16      	taddr_l;            /* temp address (LSB) */
    } SCC_ETHER_PROTO;
 
/* SCC device descriptor */

typedef struct          /* SCC_ETHER_DEV */
    {
    int                 sccNum;         /* number of SCC device */
    int                 txBdNum;        /* number of transmit buf descriptors */
    int                 rxBdNum;        /* number of receive buf descriptors */
    SCC_BUF *           txBdBase;       /* transmit BD base address */
    SCC_BUF *           rxBdBase;       /* receive BD base address */
    u_char *            txBufBase;      /* transmit buffer base address */
    u_char *            rxBufBase;      /* receive buffer base address */
    UINT32              txBufSize;      /* transmit buffer size */
    UINT32              rxBufSize;      /* receive buffer size */
    int                 txBdNext;       /* next transmit BD to fill */
    int                 rxBdNext;       /* next receive BD to read */
    volatile SCC *      pScc;           /* SCC parameter RAM */
    volatile SCC_REG *  pSccReg;        /* SCC registers */
    UINT32              intMask;        /* interrupt acknowledge mask */
    } SCC_ETHER_DEV;

#else				/* default: use CPU32 definitions */

#define SCC_ETHER_DEV		SCC_DEV
#define CPM_DPR_SCC1(baseAddr)  M360_DPR_SCC1 (baseAddr)
#define CPM_GSMR_L1(baseAddr)   M360_CPM_GSMR_L1 (baseAddr)
#define CPM_CIMR_SCC4           CPIC_CIXR_SCC4
#define CPM_CIMR(baseAddr)      M360_CPM_CIMR (baseAddr)
#define CPM_CISR(baseAddr)      M360_CPM_CISR (baseAddr)
#define CPM_CPCR(baseAddr)      M360_CPM_CR (baseAddr)
#define END_OBJ_STRING		"MC68EN360 QUICC Enhanced Network Driver"
#define MOT_DEV_NAME "qu"
#define MOT_DEV_NAME_LEN 3

#endif /* CPU == PPC860 */

/* bsp-specific routine to include */

#if (CPU == PPC860)

#define SYS_ENET_ADDR_GET(address)                                  	\
if (sysCpmEnetAddrGet != NULL)                                          \
    if (sysCpmEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR)		\
	{								\
	errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS);			\
	return (NULL);							\
	}
 
#define SYS_ENET_ENABLE                                             	\
if (sysCpmEnetEnable != NULL)                                           \
    if (sysCpmEnetEnable (pDrvCtrl->unit) == ERROR)			\
	return (ERROR);
 
#define SYS_ENET_DISABLE                                            	\
if (sysCpmEnetDisable != NULL)                                          \
    sysCpmEnetDisable (pDrvCtrl->unit);
 
#else				/* default: use CPU32 definitions */

#define SYS_ENET_ADDR_GET(address)                                  	\
if (sys360EnetAddrGet != NULL)                                          \
    if (sys360EnetAddrGet (pDrvCtrl->unit, (address)) == ERROR)		\
	{								\
	errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS);			\
	return (NULL);							\
	}
 
#define SYS_ENET_ENABLE                                             	\
if (sys360EnetEnable != NULL)                                           \
    if (sys360EnetEnable (pDrvCtrl->unit, pDrvCtrl->regBase) == ERROR)  \
	return (ERROR);
 
#define SYS_ENET_DISABLE                                            	\
if (sys360EnetDisable != NULL)                                          \
    sys360EnetDisable (pDrvCtrl->unit, pDrvCtrl->regBase);
 
#endif /* CPU == PPC860 */

/* globals */
 
#if (CPU == PPC860)

IMPORT STATUS sysCpmEnetEnable  (int unit); /* enable ctrl */
IMPORT void   sysCpmEnetDisable (int unit); /* disable ctrl */
IMPORT STATUS sysCpmEnetAddrGet (int unit, u_char * addr);  /* get enet addr */

#else				/* default: use CPU32 prototypes */

IMPORT STATUS sys360EnetEnable  (int unit, UINT32 regBase); /* enable ctrl */
IMPORT void   sys360EnetDisable (int unit, UINT32 regBase); /* disable ctrl */
IMPORT STATUS sys360EnetAddrGet (int unit, u_char * addr);  /* get enet addr */

#endif /* CPU == PPC860 */

#ifdef	__cplusplus
}
#endif

#endif	/* __INCmotCpmEndh */