ln97xend.h

IXP425的BSP代码

#define BCR20_SWSTYLE_PCNET_II	0x0003
    
/* Control block definitions for AMD PCnet (Ethernet) chip. */

typedef struct
    {
    ULONG       rdp;            /* register data Port */
    ULONG       rap;            /* Register Address Port */
    ULONG       rst;            /* Reset Register */
    ULONG       bdp;            /* Bus Configuration Register Data Port */
    } LN_DEVICE;

/* Initialization Block */

typedef struct lnIB
    {
    ULONG       lnIBMode;       /* mode register */
    UCHAR       lnIBPadr [8];   /* PADR: bswapd ethnt phys address */
    UCHAR       lnIBLadrf [8];  /* logical address filter */
    ULONG       lnIBRdra;       /* RDRA: read ring address, long word */
    ULONG       lnIBTdra;       /* TDRA: transmit ring address long word */
    } LN_IB;

/* Receive Message Descriptor Entry.*/

typedef struct lnRMD
    {
    /* element order changed to accomodate burst mode operation */
    ULONG       lnRMD2;         /* message byte count */
    ULONG       lnRMD1;         /* status & buffer byte count (negative) */
    ULONG       lnRMD0;         /* bits 31:00 of receive buffer address */
    ULONG       lnRMD3;         /* reserved */
    } LN_RMD;

/* Transmit Message Descriptor Entry. */

typedef struct lnTMD
    {
    /* element order changed to accomodate burst mode operation */
    ULONG       lnTMD2;         /* errors */
    ULONG       lnTMD1;         /* message byte count */
    ULONG       lnTMD0;         /* bits 31:00 of transmit buffer address */
    ULONG       lnTMD3;         /* reserved */
    } LN_TMD;

typedef union addrFilter        /* logical address filter layout */
    {
    UINT8  lafBytes  [8];       /* (8) bytes */
    UINT16 lafWords  [4];       /* (4) 16-bit words */
    UINT32 lafDwords [2];       /* (2) 32-bit dwords */
    } ADDR_FILTER;

typedef enum filterModCmd       /* addrFilterMod() commands */
    {
    LN_LADRF_ADD,               /* add a logical address */
    LN_LADRF_DEL,               /* delete a logical address */
    LN_LADRF_ADD_ALL,           /* add all logical addresses */
    LN_LADRF_DEL_ALL            /* delete all logical addresses */
    } FILTER_MOD_CMD;


/* initialization block */

#define IB_MODE_TLEN_MSK	0xf0000000
#define IB_MODE_RLEN_MSK	0x00f00000

/* receive descriptor */

#define RMD1_OWN		0x80000000	/* Own */
#define RMD1_ERR		0x40000000	/* Error */
#define RMD1_FRAM		0x20000000	/* Framming Error */
#define RMD1_OFLO		0x10000000	/* Overflow */
#define RMD1_CRC		0x08000000	/* CRC */
#define RMD1_BUFF		0x04000000	/* Buffer Error */
#define RMD1_STP		0x02000000	/* Start of Packet */
#define RMD1_ENP		0x01000000	/* End of Packet */
#define RMD1_RES		0x00ff0000	/* reserved */
#define RMD1_CNST		0x0000f000	/* rmd1 constant value */

#define RMD1_BCNT_MSK		0x00000fff	/* buffer cnt mask */
#define RMD2_MCNT_MSK		0x00000fff	/* message buffer cnt mask */

/* transmit descriptor */

#define TMD1_OWN		0x80000000	/* Own */
#define TMD1_ERR		0x40000000	/* Error */
#define TMD1_MORE		0x10000000	/* More than One Retry */
#define TMD1_ONE		0x08000000	/* One Retry */
#define TMD1_DEF		0x04000000	/* Deferred */
#define TMD1_STP		0x02000000	/* Start of Packet */
#define TMD1_ENP		0x01000000	/* End of Packet */
#define TMD1_BPE                0x00800000      /* Bus Parity Error */
#define TMD1_RES		0x007F0000	/* Reserved locations */
#define TMD1_CNST		0x0000f000	/* tmd1 constant value */

#define TMD2_BUFF		0x80000000	/* Buffer Error */
#define TMD2_UFLO		0x40000000	/* Underflow Error */
#define TMD2_LCOL		0x10000000	/* Late Collision */
#define TMD2_LCAR		0x08000000	/* Lost Carrier */
#define TMD2_RTRY		0x04000000	/* Retry Error */
#define TMD2_TDR		0x03FF0000	/* Time Domain Reflectometry */

#define TMD1_BCNT_MSK		0x00000fff	/* buffer cnt mask */

/* CRC for logical address filter */

#define LN_CRC_POLYNOMIAL       (0xedb88320)    /* Ethernet CRC polynomial */
#define LN_CRC_TO_LAF_IX(crc)   ((crc) >> 26)   /* get 6 MSBits */
#define LN_LAF_LEN              (8)             /* logical addr filter length */
#define LN_LA_LEN               (6)             /* logical address length */
#define BITS_PER_LA             (8 * LN_LA_LEN) /* logical addr length bits */

/* Definitions for the drvCtrl specific flags field */

#define LS_PROMISCUOUS_FLAG     0x1     /* set the promiscuous mode */
#define LS_MEM_ALLOC_FLAG       0x2     /* allocating memory flag */
#define LS_PAD_USED_FLAG        0x4     /* padding used flag */
#define LS_RCV_HANDLING_FLAG    0x8     /* handling recv packet */
#define LS_START_OUTPUT_FLAG    0x10    /* trigger output flag */
#define LS_POLLING              0x20    /* polling flag */
#define LS_MODE_MEM_IO_MAP      0x100   /* device registers memory mapped */
#define LS_MODE_DWIO            0x200   /* device in 32 bit mode */
#define LS_MODE_NOSWAP_MASTER	0x400   /* don't swap PCI master I/O ops */

/* descriptor size */

#define RMD_SIZ                 sizeof(LN_RMD)
#define TMD_SIZ                 sizeof(LN_TMD)
#define IB_SIZ                  sizeof(LN_IB)

/* The definition of the driver control structure */

typedef struct ln97xDevice
    {
    END_OBJ           endObj;            /* The class we inherit from */

    int               unit;              /* unit number of the device */
    volatile LN_IB *  ib;                /* ptr to Initialization Block */

    int               rmdIndex;          /* current RMD send index */
    int               rringSize;         /* RMD ring size */
    int               rringLen;          /* RMD ring length (bytes) */
    volatile LN_RMD * pRring;            /* RMD ring start */

    int               tmdIndex;          /* current TMD transmit index */
    int               tmdIndexC;         /* current TMD cleaning index */
    int               tringSize;         /* TMD ring size */
    int               tringLen;          /* TMD ring length (bytes) */
    volatile LN_TMD * pTring;            /* TMD ring start */

    int               inum;              /* interrupt number */
    int               ilevel;            /* interrupt level */

    volatile UINT32 * pRdp;              /* device register CSR */
    volatile UINT32 * pRap;              /* device register RAP */
    volatile UINT32 * pReset;            /* device register Reset */
    volatile UINT32 * pBdp;              /* device register BCR */

    volatile char *   pShMem;            /* real ptr to shared memory */
    volatile char *   memBase;           /* PCnet memory pool base */
    volatile char *   memAdrs;           /* PCnet memory pool base */

    UINT32            devAdrs;           /* device structure address */
    UINT16            csr3B;             /* csr3 value board specific */
    UINT32            chipId;            /* (csr88|csr89) chip ID value */
    int               memSize;           /* PCnet memory pool size */
    int               memWidth;          /* width of data port */
    int               offset;            /* offset of data in the buffer */
    volatile UINT32   flags;             /* Our local flags */
    UINT32            pciMemBase;        /* memory base as seen from PCI*/
    UINT8             enetAddr[6];       /* ethernet address */
    CACHE_FUNCS       cacheFuncs;        /* cache function pointers */

    volatile BOOL     txBlocked;         /* transmit flow control */
    volatile BOOL     txCleaning;        /* transmit descriptor cleaning */

    CL_POOL_ID        pClPoolId;         /* cluster pool Id */
    M_CL_CONFIG       mClCfg;            /* mBlk & cluster config structure */
    CL_DESC           clDesc;            /* cluster descriptor table */

    END_ERR           lastError;         /* Last error passed to muxError */
    volatile BOOL     errorHandling;     /* task level error handling */

    } LN_97X_DRV_CTRL;

/* Configuration items */

#define LN_MIN_FBUF             (100)     /* Min sizeof first buffer in chain */
#define LN_BUFSIZ               (ETHERMTU + SIZEOF_ETHERHEADER + 6)
#define LN_SPEED                (10000000)
#define LN_RMD_RLEN             (7)       /* ring size as a ^ 2 => 128 RMD's */
#define LN_TMD_TLEN             (7)       /* ring size as a ^ 2 => 128 TMD's */
#define LN_RMD_MIN              (2)       /* min descriptors 4 */
#define LN_TMD_MIN              (2)       /* min descriptors 4 */
#define LN_RMD_MAX              (9)       /* max descriptors 512 */
#define LN_TMD_MAX              (9)       /* max descriptors 512 */
#define LN_97X_DEV_NAME         "lnPci"   /* name of the device */
#define LN_97X_DEV_NAME_LEN     (6)       /* length of the name string */
#define LN_97X_APROM_SIZE       (32)      /* hardware Address PROM size bytes */
#define LN_LITTLE_ENDIAN        (0)       /* little endian PCI bus      */
#define LN_BIG_ENDIAN           (1)       /* big endian PCI bus         */
#define LN_ACTIVE_LOW           (0)       /* active-low interrupt line  */
#define LN_ACTIVE_HI            (1)       /* active-high interrupt line */

#define LN_RMD_OWNED(rmd)       (PCI_SWAP ((rmd)->lnRMD1) & RMD1_OWN)
#define LN_TMD_OWNED(tmd)       (PCI_SWAP ((tmd)->lnTMD1) & TMD1_OWN)

#define LN_PKT_LEN_GET(rmd)     (PCI_SWAP ((rmd)->lnRMD2) - 4)


#if defined(__STDC__) || defined(__cplusplus)

IMPORT STATUS    ln97xInitParse (LN_97X_DRV_CTRL * pDrvCtrl, char * initString);
IMPORT END_OBJ * ln97xEndLoad (char * initString);

#else

IMPORT STATUS    ln97xInitParse ();
IMPORT END_OBJ * ln97xEndLoad ();

#endif  /* __STDC__ */

#endif  /* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif /* __INCln97xEndh */