sh7615end.h

IXP425的BSP代码

#define TRSCER_ITFCE	0x00001000	/* Illegal Tx Frame */
#define TRSCER_CNDCE	0x00000800	/* Carrier not detected */
#define TRSCER_DLCCE	0x00000400	/* Detect loss of carrier */
#define TRSCER_CDCE	0x00000200	/* Collision Detect */
#define TRSCER_TROCE	0x00000100	/* Tx Retry Over */
#define TRSCER_RMAFCE	0x00000080	/* Receive Multicast Address frame */
#define TRSCER_RRFCE	0x00000010	/* Receive residual-bit frame */
#define TRSCER_RTLFCE	0x00000008	/* Receive Too-long frame */
#define TRSCER_RTSFCE	0x00000004	/* Receive Too-short frame */
#define TRSCER_PRECE	0x00000002	/* PHY-LSI Receive Error */
#define TRSCER_CERFCE	0x00000001	/* CRC Error on Received frame */

/*
 * FIFO Depth Register
 */

/*  */

/*
 * Receiver Control Register
 */

#define RCR_RNC		0x00000001	/* Receive Enable Control */

/*
 * E-DMAC Operation Control Register
 */

#define EDOCR_FEC	0x00000004	/* FIFO Error control */
#define EDOCR_AEC	0x00000002	/* Address Error Control*/
#define EDOCR_EDH	0x00000001	/* E-DMAC Halted */

/* Transmit descriptor bit definitions */

#define TD0_TACT	0x80000000	/* Tx Descriptor Active */
#define TD0_OWN		TD0_TACT        /* the chip owns the descriptor */
#define TD0_TDL		0x40000000	/* Tx Descriptor Last */
#define TD0_TFP1	0x20000000	/* Tx Frame Position */
#define TD0_TFP0	0x10000000	/* Tx FRame Position */
#define TD0_TFP   	0x30000000      /* buffer contains entire frame */
#define TD0_TFE		0x08000000	/* Tx Frame Error */
#define TD0_TFS4	0x00000010	/* Tx Illegal Frame */
#define TD0_IF		TD0_TFS4
#define TD0_TFS3	0x00000008	/* Tx Carrier Not Detect */
#define TD0_CND		TD0_TFS3
#define TD0_TFS2	0x00000004	/* Tx Detect Loss Carrier */
#define TD0_DLC		TD0_TFS2
#define TD0_TFS1	0x00000002	/* Tx Collision Detect */
#define TD0_CD		TD0_TFS1
#define TD0_TFS0	0x00000001	/* Tx Retry Over */
#define TD0_TRO		TD0_TFS0
#define TD0_CLEAR_ERRORS_N_STATS 0xf0000000

#define SH7615END_TBS_PUT(x)      ((x) << 16) 

/* Receive descriptor bit definitions */

#define RD0_RACT	0x80000000	/* Rx Descriptor Active */
#define RD0_OWN		RD0_RACT        /* the chip owns the descriptor */
#define RD0_RDL		0x40000000	/* Rx Descriptor Last */
#define RD0_RFP1	0x20000000	/* Rx Frame Position */
#define RD0_RFP0	0x10000000	/* Rx FRame Position */
#define RD0_RFE		0x08000000	/* Rx Frame Error */
#define RD0_RFS9	0x00000200	/* Rx FIFO Overflow */
#define RD0_RFS7	0x00000080	/* Rx Multicast Addr Frame */
#define RD0_RFS4	0x00000010	/* Rx Residual-Bit FRame */
#define RD0_RFS3	0x00000008	/* Rx Too-Long Frame */
#define RD0_RFS2	0x00000004	/* Rx Too-Short Frame */
#define RD0_RFS1	0x00000002	/* Rx PHY-LSI Recv Error */
#define RD0_RFS0	0x00000001	/* Rx CRC Error on Received */

#define SH7615END_FRAME_LEN_MSK       0x0000FFFF      /* Frame length mask */
#define SH7615END_FRAME_LEN_GET(x)    ((x) & SH7615END_FRAME_LEN_MSK)

/* DP83843BVJE PHY Chip */
#define PHY_ADDR		0x01

/* DP83843BVJE Phyter MII offset registers */

#define BMCR            0x00	/* Basic Mode Control Register */
#define BMSR		0x01	/* Basic Mode status Register */
#define PHYIDR1		0x02	/* PHY Identifier register #1 */
#define PHYIDR2		0x03	/* PHY Identifier register #2 */
#define ANAR            0x04	/* Auto-Negotiation Advertisement
				   Register */
#define ANLPAR          0x05	/* Auto-Negotiation Link Partner
				   Ability Register */
#define ANER            0x06	/* Auto-Negotiation Expansion
				   Register */
#define ANNPTR          0x07	/* Auto-Negotiation Next Page TX */
/*                      0x08-0x0f  Reserved */
#define PHYSTS		0x10	/* PHY Status Register */
#define MIPSCR          0x11	/* MII Interrupt PHY Specific Control
				   Register */
#define MIPGSR		0x12	/* MII Interrupt PHY Generic Status
				   Register */
#define DCR             0x13	/* Disconnect Count Register */
#define FCSCR           0x14 	/* False Carrier Sense Counter
				   Register */
#define RECR            0x15	/* Receive Error Counter Register */
#define PCSR            0x16	/* PCS Sub-Layer Configuration and
				   Status Register */
#define LBR             0x17 	/* Loopback and Bypass Register */
#define BTSCR           0x18	/* 10Base-T Status & Control Register */
#define PHYCTRL         0x19	/* PHY Control Register */
/*			0x1A-0x1F  Reserved */

/* DP83843BVJE Phyter MII register data */

#define	D_RESET		0x8000
#define D_BMCR          0x0000  
#define D_ANAR          0x01e1  
#define D_ANLPAR        0x0021  
#define D_ANER          0x0004 
#define D_ANNPTR        0x2001
#define D_MIPSCR        0x0000
#define D_DCR           0x0000
#define D_FCSCR         0x0000
#define D_RECR          0x0000
#define D_PCSR          0x0000
#define D_LBR           0x0000
#define D_10BTSCR       0x0000
				
#define D_PHYCTRL       0x0801

/*
 * Receive Message Descriptor Entry.
 * Four words per entry.  Number of entries must be a power of two.
 */
typedef struct rDesc
    {
    UINT32       rDesc0;         /* status */
    UINT32       rDesc1;         /* buffer & data count */
    UINT32       rDesc2;         /* buffer address 1 */
    UINT32       rDesc3;         /* Pad */
    } SH7615_RD;
 
/*
 * Transmit Message Descriptor Entry.
 * Four words per entry.  Number of entries must be a power of two.
 */
typedef struct tDesc
    {
    UINT32       tDesc0;         /* status */
    UINT32       tDesc1;         /* data count */
    UINT32       tDesc2;         /* buffer address 1 */
    UINT32       tDesc3;         /* Pad */
    } SH7615_TD;

typedef struct free_buf
    {
    void *      pClBuf;                  /* pointer cluster buffer */
    } FREE_BUF;
 
/* typedefs */
 
typedef struct sh7615EndDrvCtrl
    {
    END_OBJ     end;                    /* The class we inherit from. */
    END_ERR	lastError;		/* Last error passed to muxError */
    long        flags;                  /* Our local flags. */
    ULONG       userFlags;              /* some user flags */
    int         unit;                   /* unit number */
 
    int         numRds;                 /* RD ring size */
    int         rxIndex;               /* current RMD index */
    SH7615_RD*  rxRing;                 /* RMD ring start */
 
    int         numTds;                 /* TD ring size */
    int         txIndex;               /* current TMD index */
    int         txDiIndex;              /* current TMD index */
    SH7615_TD*  txRing;                 /* TMD ring start */
 
    int         ivec;                   /* interrupt vector */
    int         ilevel;                 /* interrupt level */
    UINT32      intrMask;               /* interrupt mask */
    char*       pShMem;                 /* real ptr to shared memory */
    char*       memBase;                /* LANCE memory pool base */
    int         memSize;                /* LANCE memory pool size */
 
    BOOL        loaded;                 /* interface has been loaded */
    char *      pClBlkArea;             /* cluster block pointer */
    UINT32      clBlkSize;              /* clusters block memory size */
    char *      pMBlkArea;              /* mBlock area pointer */
    UINT32      mBlkSize;               /* mBlocks area memory size */
    UCHAR       enetAddr[6];            /* ethernet address */
    CL_POOL_ID  pClPoolId;              /* cluster pool */
    BOOL        rxHandling;             /* rcv task is scheduled */
    BOOL        txCleaning;
    BOOL        txBlocked;              /* variable for blocking */
/* REVISIT - shouldn't this be the same array size as number of possible buffers? */
    FREE_BUF    freeBuf[128];
/*    PHY_INFO    *phyInfo;  */             /* info on a MII-compliant PHY */
    } SH7615END_DRV_CTRL;
 
/* rx/tx buffer descriptors definitions */

#define SH7615END_RBD_SZ          16      /* RBD size in byte */
#define SH7615END_TBD_SZ          16      /* TBD size in byte */
#define SH7615END_TBD_MIN         6       /* min number of TBDs */
#define SH7615END_RBD_MIN         4       /* min number of RBDs */
#define SH7615END_TBD_POLL_NUM    1       /* one TBD for poll operation */
#define CL_OVERHEAD               4       /* prepended cluster overhead */
#define CL_ALIGNMENT              4       /* cluster required alignment */
#define MBLK_ALIGNMENT            4       /* mBlks required alignment */
#define SH7615END_BD_ALIGN        0x10    /* required alignment for RBDs */
#define SH7615END_MAX_PCK_SZ      (ETHERMTU + SIZEOF_ETHERHEADER          \
                                 + ETHER_CRC_LEN)

#define SH7615END_RBD_DEF_NUM  48      /* default number of Recv descriptors */
#define SH7615END_TBD_DEF_NUM  64      /* default number of Xmit descriptors */
#define NUM_LOAN        16      /* number of loaner buffers */

#ifdef __cplusplus
}
#endif
 
#endif /* __INCsh7615Endh */