sh7615end.h

IXP425的BSP代码

/* sh7615End.h - Ethernet driver header */
 
/* Copyright 1984-2000 Wind River Systems, Inc. */
 
/*
modification history
--------------------
01j,28mar02,h_k  added lastError in SH7615END_DRV_CTRL (SPR #74021).
01i,02nov00,frf  changed macros definitions for PHY registers.
01h,26sep00,rsh  remove some macros related to allowing bsp to provide shared
                 memory
01g,25sep00,rsh  add macro defs for reading and writing registers a'la
                 motFecEnd
01f,25sep00,rsh  add some additional macros that make code more readable
01e,22sep00,rsh  continue development
01d,14sep00,rsh  continue development
01c,18aug00,rsh  continue developement
01b,16aug00,rsh  continue development
01a,14aug00,rsh   written 
*/
 
#ifndef __INCsh7615Endh
#define __INCsh7615Endh
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* driver flags */


/* Ethernet Controller register offsets */

#define ETHERC_ECMR		0xFFFFFD60	/* R/W: EtherC mode register */
#define ETHERC_ECSR		0xFFFFFD64	/* R/W: EtherC status register */
#define ETHERC_ECSIPR		0xFFFFFD68	/* R/W: EtherC status int permission */
#define ETHERC_PIR		0xFFFFFD6C	/* R/W: PHY Interface register */
#define ETHERC_MAHR		0xFFFFFD70	/* R/W: MAC Address High register */
#define ETHERC_MALR		0xFFFFFD74	/* R/W: MAC Address Low register */
#define ETHERC_RFLR		0xFFFFFD78	/* R/W: Receive frame length register */
#define ETHERC_PSR		0xFFFFFD7C	/* R:   PHY status register */
#define ETHERC_TROCR		0xFFFFFD80	/* R/W: Tx retry over counter register */
#define ETHERC_CDCR		0xFFFFFD84	/* R/W: Collision detect counter register */
#define ETHERC_LCCR		0xFFFFFD88	/* R/W: Lost Carrier counter register */
#define ETHERC_CNDCR		0xFFFFFD8C	/* R/W: Carrier not detect counter */
#define ETHERC_IFLCR		0xFFFFFD90	/* R/W: Illegal frame length counter */
#define ETHERC_CEFCR		0xFFFFFD94	/* R/W: CRC error frame recv counter */
#define ETHERC_FRECR		0xFFFFFD98	/* R/W: Frame receive error counter */
#define ETHERC_TSFRCR		0xFFFFFD9C	/* R/W: Too-short Frame recv counter */
#define ETHERC_TLFRCR		0xFFFFFDA0	/* R/W: Too-long Frame recv counter */
#define ETHERC_RFCR		0xFFFFFDA4	/* R/W: Residual bit frame counter */
#define ETHERC_MAFCR		0xFFFFFDA8	/* R/W: Multicast addr frame counter */

/* E-DMAC registers */

#define E_DMAC_EDMR		0xFFFFFD00	/* R/W: E-DMAC mode register */
#define E_DMAC_EDTRR		0xFFFFFD04	/* R/W: E-DMAC tran request register */
#define E_DMAC_EDRRR		0xFFFFFD08	/* R/W: E-DMAC recv request register */
#define E_DMAC_TDLAR		0xFFFFFD0C	/* R/W: Tx desc list addr register */
#define E_DMAC_RDLAR		0xFFFFFD10	/* R/W: Rx desc list addr register */
#define E_DMAC_EESR		0xFFFFFD14	/* R/W: EtherC/E-DMAC status register */
#define E_DMAC_EESIPR		0xFFFFFD18	/* R/W: EtherC/E-DMAC status interrupt
                                                                   permission register */
#define E_DMAC_TRSCER		0xFFFFFD1C	/* R/W: Tx/Rx status copy enable */  
#define E_DMAC_RMFCR		0xFFFFFD20	/* R/W: Recevied missed-frame counter */  
#define E_DMAC_TFTR		0xFFFFFD24	/* R/W: Tx FIFO threshold register */  
#define E_DMAC_FDR		0xFFFFFD28	/* R/W: FIFO depth register */  
#define E_DMAC_RCR		0xFFFFFD2C	/* R/W: Receiver control register */  
#define E_DMAC_EDOCR		0xFFFFFD30	/* R/W: E-DMAC operation control */  

/* Ethernet Controller register bit definitions */

/*
 * EtherC mode Register bits
 */

#define ECMR_PRCEF	0x00001000 	/* Permit Receive CRC Error Frame */
#define ECMR_MPDE	0x00000200	/* Magic Packet Detection enable */
#define ECMR_RE		0x00000040	/* Receiver Enable */
#define ECMR_TE		0x00000020	/* Transmitter Enable */
#define ECMR_ILB	0x00000008	/* Internal loop back mode */
#define ECMR_ELB	0x00000004	/* External loop back mode */
#define ECMR_DM		0x00000002	/* Duplex Mode */
#define ECMR_PRM	0x00000001	/* Promiscuous Mode */

/*
 * EtherC Status Register
 */

#define ECSR_LCHNG	0x00000004	/* LINK signal changed */
#define ECSR_MPR	0x00000002	/* Magic Packet received */
#define ECSR_ICD	0x00000001	/* Illegal Carrier detection */
#define ECSR_CLEAR	0x00000007      /* clear all sources */

/* 
 * EtherC Status Interrupt Permission Register
 */

#define ECSIPR_LCHNGIP	0x00000004	/* LINK signal change int enable */
#define ECSIPR_MPRIP	0x00000002	/* Magic Packet received int enable */
#define ECSIPR_ICDIP	0x00000001	/* Illegal Carrier detection int enalbe */
#define ECSIPR_CLEAR    0x00000000	/* Disable all sources */

/* 
 * PHY Interface Register
 */

#define PIR_MDI		0x00000008	/* MII Management Data-In */
#define PIR_MDO		0x00000004	/* MII Management Data-Out */
#define PIR_MMD		0x00000002	/* MII Management Data Mode */
#define PIR_MDC		0x00000001	/* MII Management Data Clock */

/*
 * Receive Frame Length Register
 */

#define RFLR_1518	0x000005ee	/* 1518 bytes */
#define RFLR_1519	0x000005ef	/* 1519 bytes */
#define RFLR_1520	0x000005f0	/* 1520 bytes */
#define RFLR_2047	0x000007ff	/* 2047 bytes */
#define RFLR_2048	0x00000800	/* 2048 bytes */

/*
 * PHY Interface Status Register
 */

#define PSR_LMON	0x00000001	/* Link Monitor */

/*
 * counter register clear macros
 */

#define TXROC_CLEAR	0x0000FFFF	/* clear counter */
#define CDCR_CLEAR	0x0000FFFF	/* clear counter */
#define LCCR_CLEAR	0x0000FFFF	/* clear counter */
#define CNDCR_CLEAR	0x0000FFFF	/* clear counter */
#define IFLCR_CLEAR	0x0000FFFF	/* clear counter */
#define CEFCR_CLEAR	0x0000FFFF	/* clear counter */
#define FRECR_CLEAR	0x0000FFFF	/* clear counter */
#define TSFRCR_CLEAR	0x0000FFFF	/* clear counter */
#define TLFRCR_CLEAR	0x0000FFFF	/* clear counter */
#define RFCR_CLEAR	0x0000FFFF	/* clear counter */
#define MAFCR_CLEAR	0x0000FFFF	/* clear counter */

/* E-DMAC register bit definitions */

/*
 * E-DMAC Mode Register 
 */

#define EDMR_DL1	0x00000020	/* Descriptor length */
#define EDMR_DL0	0x00000010	/* Descriptor length */
#define EDMR_SWR	0x00000001	/* Software reset */

/* 
 * E-DMAC Transmit request register 
 */

#define EDTRR_TR	0x00000001	/* Transmit request */

/* 
 * E-DMAC Receive request register 
 */

#define EDRRR_RR	0x00000001	/* Receive request */

/* 
 * EtherC/E-DMAC status register
 */

#define EESR_RFCOF	0x01000000	/* Receive frame counter overflow */ 
#define EESR_ECI	0x00400000	/* EtherC status regsiter interrupt */ 
#define EESR_TC		0x00200000	/* Tx Complete */ 
#define EESR_TDE	0x00100000 	/* Tx Descriptor Exhausted */
#define EESR_TFUF	0x00080000	/* Tx FIFO Underflow */ 
#define EESR_FR		0x00040000	/* Frame Received */ 
#define EESR_RDE	0x00020000	/* Rx Descriptor Exhausted */ 
#define EESR_RFOF	0x00010000	/* Rx FIFO Overflow */ 
#define EESR_ITF	0x00001000	/* Illegal Tx Frame */ 
#define EESR_CND	0x00000800	/* Carrier not detected */ 
#define EESR_DLC	0x00000400	/* Detect loss of carrier */ 
#define EESR_CD		0x00000200	/* Collision Detect */ 
#define EESR_TRO	0x00000100	/* Tx Retry Over */ 
#define EESR_RMAF	0x00000080	/* Receive Multicast Address frame */ 
#define EESR_RRF	0x00000010	/* Receive residual-bit frame */ 
#define EESR_RTLF	0x00000008	/* Receive Too-long frame */ 
#define EESR_RTSF	0x00000004	/* Receive Too-short frame */ 
#define EESR_PRE	0x00000002	/* PHY-LSI Receive Error */ 
#define EESR_CERF	0x00000001	/* CRC Error on Received frame */ 

#define EESR_VALID_INT_MSK 0x017f1f9f   /* all possible interrupt sources */
#define EESR_CLEAR         0x017f1f9f   /* all possible interrupt sources */

/* 
 * EtherC/E-DMAC status Interrupt Permission register
 */

#define EESIPR_RFCOFIP	0x01000000	/* Receive frame counter overflow */ 
#define EESIPR_ECIIP	0x00400000	/* EtherC status regsiter interrupt */ 
#define EESIPR_TCIP	0x00200000	/* Tx Complete */ 
#define EESIPR_TDEIP	0x00100000 	/* Tx Descriptor Exhausted */
#define EESIPR_TFUFIP	0x00080000	/* Tx FIFO Underflow */ 
#define EESIPR_FRIP	0x00040000	/* Frame Received */ 
#define EESIPR_RDEIP	0x00020000	/* Rx Descriptor Exhausted */ 
#define EESIPR_RFOFIP	0x00010000	/* Rx FIFO Overflow */ 
#define EESIPR_ITFIP	0x00001000	/* Illegal Tx Frame */ 
#define EESIPR_CNDIP	0x00000800	/* Carrier not detected */ 
#define EESIPR_DLCIP	0x00000400	/* Detect loss of carrier */ 
#define EESIPR_CDIP	0x00000200	/* Collision Detect */ 
#define EESIPR_TROIP	0x00000100	/* Tx Retry Over */ 
#define EESIPR_RMAFIP	0x00000080	/* Receive Multicast Address frame */ 
#define EESIPR_RRFIP	0x00000010	/* Receive residual-bit frame */ 
#define EESIPR_RTLFIP	0x00000008	/* Receive Too-long frame */ 
#define EESIPR_RTSFIP	0x00000004	/* Receive Too-short frame */ 
#define EESIPR_PREIP	0x00000002	/* PHY-LSI Receive Error */ 
#define EESIPR_CERFIP	0x00000001	/* CRC Error on Received frame */ 

/*
 * Tx/Rx status copy enable register 
 */