dec21x40end.h

IXP425的BSP代码

#define MII_PHY_ANLPA_HDAM	0x02a0  /* Half Duplex Technology Ability Mask */
#define MII_PHY_ANLPA_100M	0x0380  /* 100Mb Technology Ability Mask */
#define MII_PHY_ANLPA_10M	0x0060  /* 10Mb Technology Ability Mask */
#define MII_PHY_ANLPA_CSMA	0x0001  /* CSMA-CD Capable */

#define MII_PHY_SR_

/* DEC Serial ROM */

#define DEC21140_SROM_SIZE	128
#define DEC21140_SROM_WORDS	64
#define	DEC21140_SROM_VERSION_3	0x3
#define	DEC21140_SROM_VERSION_4	0x4

/* Serial ROM access macros */

#define SROM_VERSION(pSrom)		(UCHAR) *(pSrom + 0x12)
#define SROM_ILEAF0_OFFSET(pSrom)      	SROM_SHORT (pSrom + 0x1b)

/* Serial ROM Info Leaf */

#define	ILEAF_GPR_MODE(pILeaf)		(UCHAR) *(pILeaf + 2)
#define ILEAF_MEDIA_COUNT(pILeaf)	(UCHAR) *(pILeaf + 3)
#define	ILEAF_INFO_BLK0(pILeaf)		(UCHAR *) (pILeaf + 4)

/* Serial ROM Info Leaf  - 21143 */

#define ILEAF_21143_MEDIA_COUNT(pILeaf) (UCHAR) *(pILeaf + 2)
#define ILEAF_21143_INFO_BLK0(pILeaf)   (UCHAR *) (pILeaf + 3)

/* Serial ROM Info Leaf  - 21145 */

#define ILEAF_21145_MEDIA_COUNT(pILeaf) (UCHAR) *(pILeaf + 2)
#define ILEAF_21145_INFO_BLK0(pILeaf)   (UCHAR *) (pILeaf + 3)

/* Serial ROM Info Block */

#define	IBLK_COMPACT_SIZE		4
#define IBLK_IS_COMPACT(pIBlk)		((*(pIBlk) & 0x80) == 0x00)
#define	IBLK_IS_EXT(pIBlk)		((*(pIBlk) & 0x80) == 0x80)
#define IBLK_IS_EXT0(pIBlk)                                             \
	    (IBLK_IS_EXT(pIBlk) && (IBLK_EXT_TYPE(pIBlk) == 0x00))

#define IBLK_IS_EXT1(pIBlk)		                                \
	    (IBLK_IS_EXT(pIBlk) && (IBLK_EXT_TYPE(pIBlk) == 0x01))


#define IBLK_COMPACT_MCODE(pIBlk)	(UCHAR) (*pIBlk & 0x7F)
#define	IBLK_COMPACT_GPDATA(pIBlk)	(UCHAR) *(pIBlk+1)
#define IBLK_COMPACT_CMD(pIBlk)		SROM_SHORT(pIBlk+2)

#define IBLK_EXT_SIZE(pIBlk)		(UCHAR) (*(pIBlk+0) & 0x7F)
#define IBLK_EXT_TYPE(pIBlk)		(UCHAR) *(pIBlk+1)

#define IBLK_IS_EXT2    0x02    /* Block type 2 */
#define IBLK_IS_EXT3    0x03    /* Block type 3 */
#define IBLK_IS_EXT4    0x04    /* Block type 4 */
#define IBLK_IS_EXT5    0x05    /* Block type 5 */
#define IBLK_IS_EXT7    0x07    /* Block type 7 */


#define IBLK_EXT0_TO_COMPACT(pIBlk)	(UCHAR *)(pIBlk+2)
#define IBLK_EXT1_PHY(pIBlk)		(UCHAR) *(pIBlk+2)
#define	IBLK_EXT1_INIT_LEN(pIBlk)	(UCHAR) *(pIBlk+3)
#define	IBLK_EXT1_INIT_STR(pIBlk)	(UCHAR *)(pIBlk+4)
#define	IBLK_EXT1_RESET_LEN(pIBlk)                                           \
    (UCHAR) *(IBLK_EXT1_INIT_STR(pIBlk) + IBLK_EXT1_INIT_LEN(pIBlk))
#define IBLK_EXT1_RESET_STR(pIBlk)	                                     \
    (UCHAR *) (IBLK_EXT1_INIT_STR(pIBlk) + IBLK_EXT1_INIT_LEN(pIBlk) + 1)
#define IBLK_EXT1_MEDIA_CAP(pIBlk)                                           \
    SROM_SHORT( IBLK_EXT1_RESET_STR(pIBlk) + IBLK_EXT1_RESET_LEN(pIBlk))
#define IBLK_EXT1_AUTO_AD(pIBlk)                                             \
    SROM_SHORT( IBLK_EXT1_RESET_STR(pIBlk) + IBLK_EXT1_RESET_LEN(pIBlk) + 2)
#define	IBLK_EXT1_FD_MAP(pIBlk)                                              \
    SROM_SHORT( IBLK_EXT1_RESET_STR(pIBlk) + IBLK_EXT1_RESET_LEN(pIBlk) + 4)
#define IBLK_EXT1_TTM_MAP(pIBlk)                                             \
    SROM_SHORT( IBLK_EXT1_RESET_STR(pIBlk) + IBLK_EXT1_RESET_LEN(pIBlk) + 6)

/* Extended format - Block type 2, 3, 4 & 5 - 21143 */

#define IBLK_EXT2_MCODE(pIBlk)		(UCHAR) (*(pIBlk + 2) & 0x3F)
#define IBLK_EXT2_EXT(pIBlk)		(UCHAR) ((*(pIBlk + 2) & 0x40) >> 6)
#define IBLK_EXT2_MSD_CSR13(pIBlk)      SROM_SHORT(pIBlk + 3)
#define IBLK_EXT2_MSD_CSR14(pIBlk)      SROM_SHORT(pIBlk + 5)
#define IBLK_EXT2_MSD_CSR15(pIBlk)      SROM_SHORT(pIBlk + 7)
#define	IBLK_EXT2_GPC(pIBlk)						    \
    SROM_SHORT( pIBlk + 3 + ((((UCHAR) *pIBlk) & 0x7F) - 0x6))
#define IBLK_EXT2_GPD(pIBlk)						    \
    SROM_SHORT( pIBlk + 5 + ((((UCHAR) *pIBlk) & 0x7F) - 0x6))

#define IBLK_EXT3_PHY(pIBlk)            (UCHAR) *(pIBlk+2)
#define IBLK_EXT3_INIT_LEN(pIBlk)       (UCHAR) *(pIBlk+3)
#define IBLK_EXT3_INIT_STR(pIBlk)       (UCHAR *)(pIBlk+4)
#define IBLK_EXT3_RESET_LEN(pIBlk)                                           \
    (UCHAR) *(IBLK_EXT3_INIT_STR(pIBlk) + IBLK_EXT3_INIT_LEN(pIBlk))
#define IBLK_EXT3_RESET_STR(pIBlk)                                           \
    (UCHAR *) (IBLK_EXT3_INIT_STR(pIBlk) + IBLK_EXT3_INIT_LEN(pIBlk) + 1)
#define IBLK_EXT3_MEDIA_CAP(pIBlk)                                           \
    SROM_SHORT( IBLK_EXT3_RESET_STR(pIBlk) + IBLK_EXT3_RESET_LEN(pIBlk))
#define IBLK_EXT3_AUTO_AD(pIBlk)                                             \
    SROM_SHORT( IBLK_EXT3_RESET_STR(pIBlk) + IBLK_EXT3_RESET_LEN(pIBlk) + 2)
#define IBLK_EXT3_FD_MAP(pIBlk)                                              \
    SROM_SHORT( IBLK_EXT3_RESET_STR(pIBlk) + IBLK_EXT3_RESET_LEN(pIBlk) + 4)
#define IBLK_EXT3_TTM_MAP(pIBlk)                                             \
    SROM_SHORT( IBLK_EXT3_RESET_STR(pIBlk) + IBLK_EXT3_RESET_LEN(pIBlk) + 6)
#define IBLK_EXT3_MII_CI(pIBlk)                                             \
    SROM_SHORT( IBLK_EXT3_RESET_STR(pIBlk) + IBLK_EXT3_RESET_LEN(pIBlk) + 8)

#define IBLK_EXT4_MCODE(pIBlk)		(UCHAR) (*(pIBlk + 2) & 0x3F)
#define	IBLK_EXT4_GPC(pIBlk)		SROM_SHORT(pIBlk + 3 )
#define	IBLK_EXT4_GPD(pIBlk)		SROM_SHORT(pIBlk + 5 )
#define	IBLK_EXT4_CMD(pIBlk)		SROM_SHORT(pIBlk + 7 )
#define	IBLK_EXT4_CMD_PS		0x0001
#define	IBLK_EXT4_CMD_TTM		0x0010
#define	IBLK_EXT4_CMD_PCS		0x0020
#define	IBLK_EXT4_CMD_SCR		0x0040

#define IBLK_EXT5_RESET_LEN(pIBlk)	(UCHAR) *(pIBlk+2)

#define	IBLK_EXT7_ANALOG_CTRL(pIBlk)	SROM_SHORT(pIBlk + 2 ) 
#define	IBLK_EXT7_CTRL_LOW(pIBlk)	(UCHAR) *(pIBlk + 4 ) 
#define	IBLK_EXT7_CTRL_HI(pIBlk)	(UCHAR) *(pIBlk + 5 ) 
#define	IBLK_EXT7_NOISE(pIBlk)		(UCHAR) *(pIBlk + 6 ) 
#define	IBLK_EXT7_NSE_FLOOR(pIBlk)	(UCHAR) *(pIBlk + 7 ) 
#define	IBLK_EXT7_NSE_CEILING(pIBlk)	(UCHAR) *(pIBlk + 8 ) 
#define	IBLK_EXT7_NSE_ATTACK(pIBlk)	(UCHAR) *(pIBlk + 9 ) 
#define	IBLK_EXT7_EXTRA_INDEX(pIBlk)    (UCHAR) (0x1f & *(pIBlk))  
#define	IBLK_EXT7_EXTRA_DATA(pIBlk)     (UCHAR) *(pIBlk +1 )  

/* Serial ROM Compact Info Block, command field */

#define COMPACT_CMD_ACT_INV	0x8000       /* Active Invalid */
#define	COMPACT_CMD_MED_DEF	0x4000       /* Default Media */
#define	COMPACT_CMD_POLARITY	0x0080       /* Media bit polarity */
#define COMPACT_CMD_SCR		0x0040       /* Scrambler mode */
#define	COMPACT_CMD_PCS		0x0030       /* PCS Function */
#define	COMPACT_CMD_MED_SENSE	0x000E       /* Media Sense */
#define	COMPACT_CMD_PS		0x0001       /* Port Select */

/* Serial ROM EXT1 Info Block, valid media types */

#define EXT1_MEDIA_100BT4	0x0200
#define EXT1_MEDIA_100BTX_FD	0x0100
#define EXT1_MEDIA_100BTX	0x0080
#define EXT1_MEDIA_10BT_FD	0x0040
#define EXT1_MEDIA_10BT		0x0020
#define	EXT1_MEDIA_CAP_MSK	0x03E0

/* Serial ROM EXT2 Info Block, valid media types */

#define EXT2_MEDIA_10TP		0x0000  /* 10baseT (Twisted Pair) */
#define EXT2_MEDIA_BNC		0x0001  /* 10base2 (BNC) */
#define EXT2_MEDIA_AUI		0x0002  /* 10base5 (AUI) */
#define EXT2_MEDIA_10FD		0x0004  /* 10baseT Full Duplex */
#define EXT2_MEDIA_HOMEPNA      0x0012  /* Home PNA */

typedef struct free_buf
    {
    void *	pClBuf;			     /* pointer cluster buffer */
    } FREE_BUF;

/* The dec21x40End driver control structure */

typedef struct dec21x40DrvCtrl
    {
    END_OBJ		endObj;              /* base class   */
    int			flags;               /* driver flags */

    int			unit;                /* unit number */
    ULONG		devAdrs;             /* IO base address */
    int			ivec;                /* interrupt vector */
    int			ilevel;              /* interrupt level */
    UINT32		intrMask;            /* interrupt mask */
    char *		memBase;             /* descriptor mempool base addr */
    ULONG		memSize;             /* descriptor mempool size */
    ULONG		pciMemBase;          /* memory base on PCI adr space */
    ULONG		usrFlags;
    ULONG		drvFlags;
    int			offset;		     /* offset to fix alignment */

    int			numRds;              /* RD ring size */
    int			rxIndex;             /* index into RD ring */
    DEC_RD *		rxRing;              /* RD ring */

    int			numTds;              /* TD ring size */
    int			txIndex;             /* index into TD ring */
    int			txDiIndex;           /* disposal index into TD ring */
    DEC_TD *		txRing;              /* TD ring */

    UINT8		mediaCount;          /* Number of PHY devices [RW] */
    UINT8		mediaDefault;        /* Default PHY device [RW] */
    UINT8		mediaCurrent;        /* Current PHY device [RW] */
    UINT8		gprModeVal;          /* Mode bits for GP register [RW]*/

    BOOL		rxHandling;
    BOOL		txCleaning;
    BOOL		intrConnect;	     /* intr routine connected */

    CACHE_FUNCS 	cacheFuncs;          /* cache function pointers */
    BOOL		txBlocked;	     /* variable for blocking */
    FREE_BUF		freeBuf[128];
    CL_POOL_ID		clPoolId;

    int			rxLen;               /* current receive bytes */
    int			rxMaxLen;            /* receive managment limit */

    PHY_INFO            *pPhyInfo;	     /* info on a MII-compliant PHY */
    UINT32		miiPhyFlags;	     /* MII-compliant PHY flags */
    UINT8		phyAddr;	     /* MII-compliant PHY address */
    MII_AN_ORDER_TBL *	pMiiPhyTbl;	     /* MII-compliant PHY's table */
    HOMEPNA_PHY_INFO    *pHomePNAPhyInfo;   /* info on a HomePNA PHY */
    BOOL                homePNAPhyValuesFound; /* existance of defaults */
    char                *txPollSendBuf;	     /* buffer for poll mode send */
    int                 loanBufs;            /* number of loaner clusters */
    } DEC21X40_DRV_CTRL;

IMPORT FUNCPTR	_func_dec21x40MediaSelect;

#define DRV_NAME		"dc"
#define DRV_NAME_LEN            3
#define EADDR_LEN		6
#define ETH_CRC_LEN		4
#define DEC_BUFSIZ		(ETHERMTU + SIZEOF_ETHERHEADER + EADDR_LEN)

/* DRV_CTRL flags */
#define DEC_MEMOWN		0x0001	/* TDs and RDs allocated by driver */
#define DEC_TX_KICKSTART	0x0002	/* No transmit poll */
#define DEC_POLLING		0x0004	/* Poll mode, io mode */
#define DEC_PROMISC		0x0008	/* Promiscuous, rx mode */
#define DEC_MCAST		0x0010	/* Multicast, rx mode */
#define DEC_BSP_EADRS		0x0020  /* Use BSP routine to get ether addr */
#define DEC_NOSWAP_MASTER	0x0040  /* Don't swap PCI bus master I/O */
#define DEC_21140		0x4000	/* DEC21140 device type */
#define DEC_21040		0x8000	/* DEC21040 device type */
#define DEC_21143		0x2000	/* DEC21143 device type */
#define DEC_21145		0x1000	/* DEC21145 device type */

/*
 * User options
 *
 * These options may be set in the userFlags field of the dec21x40End driver
 * load string. The driver, at initialization, will set up apt registers to
 * reflect the selected options.
 */

#define DEC_USR_BE	0x00000001	/* CSR0: Big Endian */

#define	DEC_USR_TAP_02	0x00000002	/* CSR0: Tx poll every 200 usec */
#define	DEC_USR_TAP_08	0x00000004	/* CSR0: Tx poll every 800 usec */
#define	DEC_USR_TAP_16	0x00000006	/* CSR0: Tx poll every 1.6 msec */
#define DEC_USR_TAP_012	0x00000008      /* CSR0: Tx poll every 12.8 usec */
#define DEC_USR_TAP_025	0x0000000A      /* CSR0: Tx poll every 25.6 usec */
#define DEC_USR_TAP_051	0x0000000C      /* CSR0: Tx poll every 51.2 usec */
#define DEC_USR_TAP_102	0x0000000E      /* CSR0: Tx poll every 102.4 usec */
#define DEC_USR_TAP_MSK 0x0000000E
#define DEC_USR_TAP_SHF	16

#define	DEC_USR_CAL_08	0x00000010	/* CSR0: Cache adrs aligned  8 lwords */
#define	DEC_USR_CAL_16	0x00000020	/* CSR0: Cache adrs aligned 16 lwords */
#define	DEC_USR_CAL_32	0x00000030	/* CSR0: Cache adrs aligned 32 lwords */
#define	DEC_USR_CAL_MSK	0x00000030
#define DEC_USR_CAL_SHF	10

#define	DEC_USR_PBL_01	0x00000040	/* CSR0: DMA burst len  1 lword */
#define	DEC_USR_PBL_02	0x00000080	/* CSR0: DMA burst len  2 lwords */
#define	DEC_USR_PBL_04	0x00000100	/* CSR0: DMA burst len  4 lwords */
#define	DEC_USR_PBL_08	0x00000200	/* CSR0: DMA burst len  8 lwords */
#define	DEC_USR_PBL_16	0x00000400	/* CSR0: DMA burst len 16 lwords */
#define	DEC_USR_PBL_32	0x00000800	/* CSR0: DMA burst len 32 lwords */
#define	DEC_USR_PBL_MSK	0x00000FC0
#define DEC_USR_PBL_SHF	2

#define	DEC_USR_BAR_RX	0x00001000	/* CSR0: Rx has priority over Tx */
#define	DEC_USR_RML	0x00002000	/* CSR0: PCI memory-read-multiple */
#define	DEC_USR_XEA	0x00004000      /* Use sysDec21x40EnetAddrGet() */
#define	DEC_USR_SF	0x00008000	/* Enable store&forward CSR6:21 */

#define DEC_USR_THR_072	0x00000000      /* Use TxTheshold 72/128 bytes */
#define	DEC_USR_THR_096 0x00010000      /* Use TxTheshold 96/256 bytes */
#define	DEC_USR_THR_128 0x00020000      /* Use TxTheshold 128/512 bytes */
#define	DEC_USR_THR_160 0x00030000      /* Use TxTheshold 160/1024 bytes */
#define DEC_USR_THR_MSK 0x00030000
#define DEC_USR_THR_SHF	2

#define DEC_USR_SB	0x00040000      /* Enable backoff counter CSR6:5 */
#define DEC_USR_PB	0x00080000	/* Enable pass bad frame  CSR6:3 */
#define DEC_USR_SC	0x00100000	/* Enable spl capture effect CSR6:31 */
#define DEC_USR_CA	0x00200000	/* Enable capture effect CSR6:17 */

/*
 * since USR_FORCE_MODE, USR_100MB, USR_FD, USR_PHY_CHK dont seem to be 
 * used anymore by the current drirver, we take over their bits for HomePNA
 */

/* FORCE HomePNA to desired modes */

#define DEC_USR_HPNA_FORCE_LOW_PWR 0x00400000 /* low power HomePNA */
#define DEC_USR_HPNA_FORCE_HI_PWR  0x00800000 /* high power HomePNA */
#define DEC_USR_HPNA_FORCE_SLOW    0x01000000 /* low speed HomePNA 0.7 MB/s */
#define DEC_USR_HPNA_FORCE_FAST    0x02000000 /* hi speed HomePNA 1 MB/s */

#define DEC_USR_MII    	   0x04000000	/* use additional pars for MII PHY */

#define DEC_USR_HPNA_PREFER_10BT   0x08000000	/* continually autonegotiate */
						/* 10BT link and select if avaliable */
#define	DEC_USR_21145	0x20000000	/* Intel/DEC 21145 part */
#define	DEC_USR_21143	0x40000000	/* DEC 21143 part */
#define	DEC_USR_21140	0x80000000	/* DEC 21140 part */
#define	DEC_USR_VER_MSK	0xE0000000	/* DEC version mask */



#define	DEC_USR_CSR6_MSK (CSR6_21140_PS | CSR6_21140_PCS | CSR6_21140_SCR | \
			  CSR6_21140_TTM | CSR6_FD | CSR6_21140_HBD)

/* Special MII flag bit definitions, not the user flag bits */

#define DEC_USR_MII_BUS_MON	0x01000000	/* monitor the MII bus */
#define DEC_USR_MII_AN_TBL	0x04000000	/* use auto-negotiation table */
#define DEC_USR_MII_NO_AN	0x08000000	/* do not auto-negotiate */
#define DEC_USR_MII_FD		0x10000000	/* allow full duplex */
#define DEC_USR_MII_100MB	0x20000000	/* allow 100 MB */
#define DEC_USR_MII_HD		0x40000000	/* allow half duplex */
#define DEC_USR_MII_10MB	0x80000000	/* allow 10 MB */


/*
 * Driver options
 *
 * These options may be set in the drvFlags field of the dec21x40End driver
 * load string.  The driver's run time behavior can be controlled by these
 * flags.
 */

#define DEC_DRV_NOSWAP_MASTER	0x00000001	/* don't swap PCI master I/O */


/*
 * Device specific network configuration defined in configNet.h
 */

IMPORT M_CL_CONFIG	dec21x40MBlkConfig;  /* mblk config description */
IMPORT CL_DESC		dec21x40ClDescTbl[]; /* cluster pool config table */
IMPORT int		dec21x40ClDescTblEnt;

#ifdef __cplusplus
}
#endif

#endif /* __INCdec21x40Endh */