dec21x40end.h

IXP425的BSP代码

/* dec21x40End.h - DEC Ethernet LAN Controller 21x40 interface header */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
03h,30may02,sru  Added REGSWAP and DEC_DRV_NOSWAP_MASTER definitions
03g,13may02,rcs  added loanBufs field to DEC21X40_DRV_CTRL SPR# 75455 
03f,22apr02,rcs  added txPollSendTd and txPollSendBuf fields to 
                 DEC21X40_DRV_CTRL SPR# 76102
03e,20jul01,rcs  added LE_BYTE_SWAP to byte swap only little endian (SPR# 69093)
03c,17jul00,ar   standardised
03c,17apr00,an   Added DEC_USR_HPNA_FORCE_FAST and SLOW flags. Add 
                 DEC_USR_HPNA_FORCE_LOW_PWR and HI_PWR flags. Removed
                 unused DEC_USR_FORCE, DEC_USR_100MB, DEC_USR_FD, and
		 DEC_USR_PHY_CHK flags.
03b,13apr00,an   Added DEC_USR_HPNA_PREFER_10BT flag to support special 
                 dec21145 media change technique.
03a,18feb00,an   Added support for 21145. Added missing 21040,21140 and 
                 21143 defines.
01w,11jun00,ham  removed reference to etherLib.
01v,08may00,jgn  SPR 31198, Added more SROM macros
01u,23mar00,dmw  Added Serial ROM EXT2 Info Block, valid media types
01t,24feb00,stv  made a selective merge to add alignment fix.
01s,06dic99,cn   re-introduced definitions of MII_READ and MII_WRITE for
		 backward compatibility (SPR #29542).
01r,08nov99,cn   Added MII-related definitions.
01q,19aug99,dmw  Added mask to IBLK_EXT_SIZE to look at only the size (0x7F).
01p,17aug99,dmw  Added defines for ANA and ANLPA registers.
01p,07apr99,dra  Added offset field for alignment fix.
01o,30mar99,dat  Fixed SROM_VERSION, SPR 26201
01n,11mar99,tm   Added CSR9/MII/21143 defines, DEC_USR_PHY_CHK flag (SPR 22196)
01m,02mar99,tm   Added intr mask to drvCtrl struct for multipass ISR (SPR 23950)
01l,18jan99,scb  Added support for END driver on dec21143.
01k,31jul98,cn   Added macro DEC_USR_FD [SPR# 21683] and field intrConnect
		 in pDrvCtrl [SPR#21557].
01j,20apr98,map  fixed endian-safe SROM_SHORT macro [SPR# 21013]
01i,24sep97,vin  changed MBLK_CONFIG to M_CL_CONFIG
01h,31aug97,vin  added a txBlocked variable to the drvCtrl structure.
01g,22aug97,gnn  changes due to new buffering scheme.
01f,21aug97,vin  modified free_buf type def added map's fixes
01e,10jun97,map  renamed funcDec21x40MediaSelect to _func_dec21x40MediaSelect.
01d,02jun97,map  added DEC Serial ROM support, and driver control definitions.
01c,24apr97,map  added PCISWAP_SHORT
01b,18apr97,map  added support for dec 21140
01a,10jan97,map  written from ../netif/if_dc.h
*/

#ifndef __INCdec21x40Endh
#define __INCdec21x40Endh

#ifdef __cplusplus
extern "C" {
#endif

#include "end.h"
#include "netBufLib.h"
#include "miiLib.h"
#include "netinet/if_ether.h"

#define DECPCI_REG_OFFSET		0x08	/* quad word aligned */

/* Endian safe macros - PCISWAP, PCISWAP_SHORT, SROM_SHORT */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#   define PCISWAP(x)		LONGSWAP(x)
#   define PCISWAP_SHORT(x)	(MSB(x) | LSB(x) << 8)
#   define LE_BYTE_SWAP(x)     (x)
#else
#   define PCISWAP(x)		(x)
#   define PCISWAP_SHORT(x)	(x)
#   define LE_BYTE_SWAP(x)  (MSB(x) | LSB(x) << 8) /* little endian byte SWAP */
#endif /* _BYTE_ORDER == _BIG_ENDIAN */

/* REGSWAP - Run-time controllable PCISWAP, for use with chip registers */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#    define REGSWAP(x)  (DRV_FLAGS_ISSET(DEC_NOSWAP_MASTER) ? \
                                (int)(x) : LONGSWAP((int)(x)))
#else
#    define REGSWAP(x)  (x)
#endif



#define SROM_SHORT(pX)		(*(UINT8*)(pX) | *((UINT8*)(pX)+1) << 8)

/*
 * Receive Message Descriptor Entry.
 * Four words per entry.  Number of entries must be a power of two.
 */

typedef struct rDesc
    {
    ULONG	rDesc0;		/* status and ownership */
    ULONG	rDesc1;		/* control & buffer count */
    ULONG	rDesc2;		/* buffer address 1 */
    ULONG	rDesc3;		/* buffer address 2 */
    } DEC_RD;

/*
 * Transmit Message Descriptor Entry.
 * Four words per entry.  Number of entries must be a power of two.
 */

typedef struct tDesc
    {
    ULONG	tDesc0;		/* status and ownership */
    ULONG	tDesc1;		/* control & buffer count */
    ULONG	tDesc2;		/* buffer address 1 */
    ULONG	tDesc3;		/* buffer address 2 */
    } DEC_TD;

#define MIN_RDS		5	/* 5 buffers reasonable minimum */
#define MIN_TDS		5	/* 5 buffers reasonable minimum */
#define NUM_RDS_DEF	32	/* default number of Recv descriptors */
#define NUM_TDS_DEF	64	/* default number of Xmit descriptors */
#define NUM_LOAN	16      /* number of loaner buffers */

/* HomePNA PHY reg */
/* maximum number of PHA PHY registers */

#define MAX_PNA_PHY_REGISTERS   0x20

/* define names to registers */

#define PNA_PHY_CTRL_LOW        0x0
#define PNA_PHY_CTRL_HI         0x1
#define PNA_PHY_STAT_LOW        0x2
#define PNA_PHY_STAT_HI         0x3
#define PNA_PHY_IMASK_LOW       0x4
#define PNA_PHY_IMASK_HI        0x5
#define PNA_PHY_ISTAT_LOW       0x6
#define PNA_PHY_ISTAT_HI        0x7
#define PNA_PHY_TX_PCOM_1       0x8
#define PNA_PHY_TX_PCOM_2       0x9
#define PNA_PHY_TX_PCOM_3       0xa
#define PNA_PHY_TX_PCOM_4       0xb
#define PNA_PHY_RX_PCOM_1       0xc
#define PNA_PHY_RX_PCOM_2       0xd
#define PNA_PHY_RX_PCOM_3       0xe
#define PNA_PHY_RX_PCOM_4       0xf
#define PNA_PHY_NOISE           0x10
#define PNA_PHY_PEAK            0x11
#define PNA_PHY_NSE_FLOOR       0x12
#define PNA_PHY_NSE_CEILING     0x13
#define PNA_PHY_NSE_ATTACK      0x14
#define PNA_PHY_NSE_EVENTS      0x15
#define PNA_PHY_AID_ADDR        0x19
#define PNA_PHY_AID_INTERVAL    0x1a
#define PNA_PHY_AID_ISBI        0x1b
#define PNA_PHY_ISBI_SLOW       0x1c
#define PNA_PHY_ISBI_FAST       0x1d
#define PNA_PHY_TX_PULSE_WIDTH  0x1e
#define PNA_PHY_TX_PULSE_CYCLES 0x1f

/* PNA PHY register bit values */

#define PHA_PHY_CTRL_LOW_PDN    0x08  /* PHY power down mode */  
#define PHA_PHY_CTRL_LOW_HS     0x04  /* PHY high speed mode */  
#define PHA_PHY_CTRL_LOW_HP     0x02  /* PHY high power mode */  

/* HomePNA SPI opcodes */

#define PNA_SPI_OPCODE_SET_WE   0x06
#define PNA_SPI_OPCODE_CLEAR_WE 0x04
#define PNA_SPI_OPCODE_READ     0x03
#define PNA_SPI_OPCODE_WRITE    0x02

/* HOMEPNA_PHY_REGS defines */

#define PNA_PHY_REG_VALUE      0x0
#define PNA_PHY_REG_UPDATED    0x1
typedef struct homePNAPhyInfo
    {
    USHORT   sp_csr13;  /* SP field for CSR13 */ 

    /* PHA phy register values */

    UCHAR    pna_phy_regs[MAX_PNA_PHY_REGISTERS][2];   
    } HOMEPNA_PHY_INFO;

/* define CSRs and descriptors */

#define CSR0	0		/* csr 0 */
#define CSR1	1		/* csr 1 */
#define CSR2	2		/* csr 2 */
#define CSR3	3		/* csr 3 */
#define CSR4	4		/* csr 4 */
#define CSR5	5		/* csr 5 */
#define CSR6	6		/* csr 6 */
#define CSR7	7		/* csr 7 */
#define CSR8	8		/* csr 8 */
#define CSR9	9		/* csr 9 */
#define CSR10	10		/* csr 10 */
#define CSR11	11		/* csr 11 */
#define CSR12	12		/* csr 12 */
#define CSR13	13		/* csr 13 */
#define CSR14	14		/* csr 14 */
#define CSR15	15		/* csr 15 */

#define RDESC0	0		/* recv desc 0 */
#define RDESC1	1		/* recv desc 1 */
#define RDESC2	2		/* recv desc 2 */
#define RDESC3	3		/* recv desc 3 */

#define TDESC0	0		/* xmit desc 0 */
#define TDESC1	1		/* xmit desc 1 */
#define TDESC2	2		/* xmit desc 2 */
#define TDESC3	3		/* xmit desc 3 */

/* command status register read write */

#define CSR(base,x)		((ULONG)(base) + ((DECPCI_REG_OFFSET) * (x)))

#define READ_CSR(base,x)	(PCISWAP(*((ULONG *)CSR((base),(x)))))

#define WRITE_CSR(base,x,val)	(*((ULONG *)CSR((base),(x))) = PCISWAP((val)))


/* recv xmit descriptor read write */

#define DESC(base,x)		((ULONG)(base) + (4 * (x)))

#define READ_DESC(base,x)	(PCISWAP(*((ULONG *)(DESC((base),(x))))))

#define WRITE_DESC(base,x,val)	(*((ULONG *)(DESC((base),(x)))) = PCISWAP((val)))


/* Definitions for fields and bits in the DEC_DEVICE */

/* CSR0 Bus Mode Register */

#define CSR0_21143_EONR	0x04000000	/* enable OnNow registers */
#define CSR0_21140_WIE	0x01000000	/* pci write and invalidate */
#define CSR0_21140_RLE	0x00800000	/* pci read line enable */
#define	CSR0_21140_RML	0x00200000	/* pci read multiple - 21140 */
#define CSR0_21140_DBO	0x00100000      /* descriptor byte ordering - 21140 */
#define CSR0_TAP_NO	0x00000000	/* no xmit auto polling */
#define CSR0_TAP_200	0x00020000	/* xmit poll every 200 usecs */
#define CSR0_TAP_800	0x00040000	/* xmit poll every 800 usecs */
#define CSR0_TAP_1600	0x00060000	/* xmit poll every 1.6 millsecs */
#define	CSR0_TAP_12	0x00080000	/* xmit poll every 12.8 usecs - 21140 */
#define	CSR0_TAP_25	0x000A0000	/* xmit poll every 25.6 usecs - 21140 */
#define	CSR0_TAP_51	0x000C0000	/* xmit poll every 51.2 usecs - 21140 */
#define	CSR0_TAP_102	0x000E0000	/* xmit poll every 102.4 usecs- 21140 */
#define CSR0_DAS	0x00010000	/* Diagnostic Address Space */
#define CSR0_CAL_NO	0x00000000	/* cache address alignment not used */
#define CSR0_CAL_08	0x00004000	/* 08 longword boundary aligned */
#define CSR0_CAL_16	0x00008000	/* 16 longword boundary aligned */
#define CSR0_CAL_32	0x0000c000	/* 32 longword boundary aligned */
#define	CSR0_PBL_UL	0x00000000	/* dma burst len - unlimited */
#define	CSR0_PBL_01	0x00000100	/* dma burst len -  1 lword */
#define	CSR0_PBL_02	0x00000200	/* dma burst len -  2 lwords */
#define	CSR0_PBL_04	0x00000400	/* dma burst len -  4 lwords */
#define	CSR0_PBL_08	0x00000800	/* dma burst len -  8 lwords */
#define	CSR0_PBL_16	0x00001000	/* dma burst len - 16 lwords */
#define	CSR0_PBL_32	0x00002000	/* dma burst len - 32 lwords */
#define CSR0_BLE	0x00000080	/* Big/little endian */
#define CSR0_BAR	0x00000002	/* Bus arbitration */
#define CSR0_SWR	0x00000001	/* software reset */

#define CSR0_PBL_MSK	0x00003F00	/* Dma burst length mask */
#define CSR0_PBL_VAL(x)	(((x) << 8) & CSR0_PBL_MSK)

#define CSR0_DSL_MSK	0x0000007C	/* Descriptor skip length */
#define CSR0_DSL_VAL(x) (((x) << 2) & CSR0_DSL_MSK)

#define CSR0_TAP_MSK	0x00060000
#define CSR0_BLE_MSK	0x00000080
#define	CSR0_CAL_MSK	0x0000c000


/* CSR1 Transmit Poll Demand Register */

#define CSR1_TPD	0x00000001	/* Transmit poll demand */

/* CSR2 Recieve Poll Demand Register */

#define CSR2_RPD	0x00000001	/* Transmit poll demand */

/* CSR3 Receive List Base address Register */

#define CSR3_RDBA_MSK	0xFFFFFFFC	/* long word aligned */
#define CSR3_RDBA_VAL(x) ((x) & CSR3_RDBA_MSK)

/* CSR4 Transmit List Base address Register */

#define CSR4_TDBA_MSK	0xFFFFFFFC	/* long word aligned */
#define CSR4_TDBA_VAL(x) ((x) & CSR4_TDBA_MSK)

/* CSR5 Status register */

#define CSR5_21145_HRI  0x10000000      /* HomePNA PHY interrupt */
#define CSR5_21143_LC   0x08000000      /* link changed */
#define CSR5_21143_GPI  0x04000000      /* general purpose port intterupt */

#define CSR5_ERR_PE	0x00000000	/* parity error */
#define CSR5_ERR_MA	0x00800000	/* Master abort */
#define CSR5_ERR_TA	0x01000000	/* target abort */

#define CSR5_TPS_ST	0x00000000	/* Stopped */
#define CSR5_TPS_RFTD	0x00100000	/* Running Fetch xmit descriptor */
#define CSR5_TPS_RWET	0x00200000	/* Running Wait for end of Xmission */
#define CSR5_TPS_RRBM	0x00300000	/* Running Read buff from memory */
#define CSR5_TPS_RSP	0x00500000	/* Running Set up packet */
#define CSR5_TPS_STFU	0x00600000	/* Suspended xmit FIFO underflow */
#define CSR5_TPS_RCTD	0x00700000	/* Running Close xmit descriptor */

#define CSR5_RPS_ST	0x00000000	/* stopped reset or stop rcv command */
#define CSR5_RPS_RFRD	0x00020000	/* Running Fetch rcv descriptor */
#define CSR5_RPS_RCEP	0x00040000	/* Running Check end of rcv packet */
#define CSR5_RPS_RWRP	0x00060000	/* Running Wait for rcv packet */
#define CSR5_RPS_SURB	0x00080000	/* Suspended - unavailable rcv buff */
#define CSR5_RPS_RCRD	0x000A0000	/* Running close rcv descriptor */
#define CSR5_RPS_RFFF	0x000C0000	/* flush frame from rcv FIFO */
#define CSR5_RPS_RQRF	0x000E0000	/* queue the rcv frame into rcv buff */

#define CSR5_NIS	0x00010000	/* normal interrupt summary */
#define CSR5_AIS	0x00008000	/* abnormal interrupt summary */
#define CSR5_SE		0x00002000	/* system error */
#define CSR5_21040_LNF	0x00001000	/* link fail - 21040 */
#define CSR5_21040_FD	0x00000800	/* Full duplex short frm rxd - 21040 */
#define	CSR5_21140_TMR	0x00000800	/* GP timer expired - 21140 */
#define CSR5_21040_AT	0x00000400	/* AUI / 10BaseT Pin - 21040 */
#define	CSR5_21140_ETI	0x00000400	/* Early Tx intrrupt - 21140 */
#define CSR5_RWT	0x00000200	/* rcv watchdog time-out */
#define CSR5_RPS	0x00000100	/* rcv process stopped */
#define CSR5_RU		0x00000080	/* rcv buffer unavailable */
#define CSR5_RI		0x00000040	/* rcv interrupt */
#define CSR5_UNF	0x00000020	/* xmit underflow */
#define CSR5_ANC	0x00000010	/* auto-negotiate complete */
#define CSR5_TJT	0x00000008	/* xmit jabber time-out */
#define CSR5_TU		0x00000004	/* xmit buffer unavailable */
#define CSR5_TPS	0x00000002	/* Xmit Process stopped */
#define CSR5_TI		0x00000001	/* xmit interrupt */

#define CSR5_RPS_MSK	0x000E0000	/* Rcv process state mask */
#define CSR5_TPS_MSK	0x00700000	/* Xmit process state mask */
#define CSR5_ERR_MSK	0x03800000	/* error mask */

/* CSR6 Operation Mode Register */

#define	CSR6_21140_SC	0x80000000	/* special capture effect enable */
#define	CSR6_21140_RA	0x40000000	/* receive all */
#define	CSR6_21145_IGDL	0x04000000	/* ignore dest addr LSB */
#define	CSR6_21143_IGDM	0x04000000	/* ignore dest addr MSB */
#define	CSR6_21140_MB1	0x02000000	/* must be 1 */
#define	CSR6_21140_SCR	0x01000000	/* scrambler mode */
#define	CSR6_21140_PCS	0x00800000	/* PCS function */
#define	CSR6_21140_TTM	0x00400000	/* tx threshold mode */