📄 gei82543end.h
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#define CTRL_MDIO_BIT CTRL_SWDPIN2_BIT#define CTRL_MDC_DIR_BIT CTRL_SWDPIO3_BIT#define CTRL_MDIO_DIR_BIT CTRL_SWDPIO2_BIT#define CTRL_SPEED_MASK 0x300#define CTRL_SWDPIOLO_SHIFT 22#define CTRL_ILOS_SHIFT 7/* Receive Control Register Fields */#define RCTL_MO_SHIFT 12#define RCTL_BSIZE_2048 0#define RCTL_BSIZE_4096 0x00030000#define RCTL_BSIZE_8192 0x00020000#define RCTL_BSIZE_16384 0x00010000#define RCTL_EN_BIT 0x00000002#define RCTL_SBP_BIT 0x00000004#define RCTL_UPE_BIT 0x00000008#define RCTL_MPE_BIT 0x00000010#define RCTL_LPE_BIT 0x00000020#define RCTL_BAM_BIT 0x00008000#define RCTL_BSEX_BIT 0x02000000/* MDI register fields */#define MDI_WRITE_BIT 0x4000000#define MDI_READ_BIT 0x8000000#define MDI_READY_BIT 0x10000000#define MDI_ERR_BIT 0x40000000#define MDI_REG_SHIFT 16#define MDI_PHY_SHIFT 21/* Flow Control Field and Initial value */#define FCRTL_XONE_BIT 0x80000000#define FLOW_CONTROL_LOW_ADR 0x00c28001#define FLOW_CONTROL_HIGH_ADR 0x00000100#define FLOW_CONTROL_TYPE 0x8808#define FLOW_CONTROL_TIMER_VALUE 0x100#define FLOW_CONTROL_LOW_THRESH 0x4000#define FLOW_CONTROL_HIGH_THRESH 0x8000/* Extended Control Register Fields */#define CTRL_EXT_SWDPIN4_BIT 0x10#define CTRL_EXT_SWDPIN5_BIT 0x20#define CTRL_EXT_SWDPIN6_BIT 0x40#define CTRL_EXT_SWDPIN7_BIT 0x80#define CTRL_EXT_SWDPIO4_BIT 0x100#define CTRL_EXT_SWDPIO5_BIT 0x200#define CTRL_EXT_SWDPIO6_BIT 0x400#define CTRL_EXT_SWDPIO7_BIT 0x800#define CTRL_EXT_SWDPIOHI_SHIFT 8#define CTRL_PHY_RESET_DIR4_BIT CTRL_EXT_SWDPIO4_BIT#define CTRL_PHY_RESET4_BIT CTRL_EXT_SWDPIN4_BIT/* Status Register Fields */#define STATUS_FD_BIT 0x1#define STATUS_LU_BIT 0x2#define STATUS_TBIMODE_BIT 0x20#define STATUS_SPEED_100_BIT 0x40#define STATUS_SPEED_1000_BIT 0x80/* TX control Regsiter Fields */#define TCTL_EN_BIT 0x2#define TCTL_PSP_BIT 0x8#define TCTL_PBE_BIT 0x800000#define TCTL_COLD_BIT 0x3ff000#define TCTL_COLD_SHIFT 12#define TCLT_CT_SHIFT 4/* TIPG Register Fields */#define TIPG_IPGR1_SHIFT 10#define TIPG_IPGR2_SHIFT 20/* RDTR Register Field */#define RDTR_FPD_BIT 0x80000000/* TX Configuration Word fields */#define TXCW_ANE_BIT 0x80000000#define TXCW_FD_BIT 0x20#define TXCW_ASM_DIR 0x100#define TXCW_PAUSE_BITS 0x180/* RXCSUM register field */#define RXCSUM_IPOFL_BIT 0x0100#define RXCSUM_TUOFL_BIT 0x0200/* PHY's Registers And Initial Value*/#define PHY_PREAMBLE 0xFFFFFFFF#define PHY_PREAMBLE_SIZE 32#define PHY_WR_OP 0x01#define PHY_RD_OP 0x02#define PHY_TURNAR 0x02#define PHY_MARK 0x01#define CL_OVERHEAD 4/* Type define */typedef struct txDescManager TX_DESCTL;typedef TX_DESCTL * P_TX_DESCTL; struct txDescManager { M_BLK_ID mBlk; /* location for mBlk */ UINT32 txType; /* TX desc type */ }; typedef struct devDrv_stat { UINT32 rxtxHandlerNum; /* num of rxtx handle routine was called per sec */ UINT32 rxIntCount; /* num of rx interrupt per sec */ UINT32 txIntCount; /* num of tx interrupt per sec */ UINT32 rxORunIntCount; /* num of rx overrun interrupt per sec */ UINT32 rxPacketNum; /* num of rx packet per sec */ UINT32 txPacketNum; /* num of tx packet per sec */ UINT32 rxPacketDrvErr; /* num of pkt rx error on driver per sec */ } DEVDRV_STAT;typedef struct dev_Timer { UINT32 rdtrVal; /* RDTR, unit of 1.024ns */ UINT32 radvVal; /* RADV, unit of 1.024us */ UINT32 itrVal; /* ITR, unit of 256 ns */ UINT32 tidvVal; /* TIDV, unit of 1.024us */ UINT32 tadvVal; /* TADV, unit of 1.024us */ UINT32 watchDogIntVal; /* interval of watchdog, unit of second */ } DEV_TIMER;struct adapter_info { int vector; /* interrupt vector */ UINT32 regBaseLow; /* register PCI base address - low */ UINT32 regBaseHigh; /* register PCI base address - high */ UINT32 flashBase; /* flash PCI base address */ BOOL adr64; /* indictor of 64 bit address */ UINT32 boardType; /* board type */ UINT32 phyType; /* PHY type (MII/GMII) */ UINT32 delayUnit; /* delay unit(in ns) for the delay function */ FUNCPTR delayFunc; /* BSP specified delay function */ STATUS (*intEnable)(int); /* board specific interrupt enable routine */ STATUS (*intDisable)(int); /* board specific interrupt disable routine */ STATUS (*intAck) (int); /* interrupt ack */ void (*phySpecInit)(PHY_INFO *, UINT8); /* vendor specified PHY's init */ UINT32 (*sysLocalToBus)(int,UINT32); UINT32 (*sysBusToLocal)(int,UINT32); FUNCPTR intConnect; /* interrupt connect function */ FUNCPTR intDisConnect; /* interrupt disconnect function */ UINT16 eeprom_icw1; /* ICW1 in EEPROM */ UINT16 eeprom_icw2; /* ICW2 in EEPROM */ UCHAR enetAddr[6]; /* Ether address for this adaptor */ UCHAR reserved1[2]; /* reserved */ FUNCPTR phyDelayRtn; /* phy delay function */ UINT32 phyMaxDelay; /* max phy detection retry */ UINT32 phyDelayParm; /* delay parameter for phy delay function */ UINT32 phyAddr; /* phy Addr */ BOOL (*sysGeiDynaTimerSetup)(struct adapter_info *); /* adjust device's timer dynamically */ BOOL (*sysGeiInitTimerSetup)(struct adapter_info *); /* set the device's timer initially */ DEVDRV_STAT devDrvStat; /* statistic data for devices */ DEV_TIMER devTimerUpdate; /* timer register value for update */ };typedef struct adapter_info ADAPTOR_INFO;/* structure for Statistic registers */typedef struct sta_reg { UINT32 crcerrs; /* CRC error count */ UINT32 algnerrc; /* alignment err count */ UINT32 symerrs; /* symbol err count */ UINT32 rxerrc; /* rx err count */ UINT32 mpc; /* missed packet count */ UINT32 scc; /* single collision count */ UINT32 ecol; /* excessive collision count */ UINT32 mcc; /* multi collision count */ UINT32 latecol; /* later collision count */ UINT32 colc; /* collision count */ UINT32 tuc; /* tx underun count */ UINT32 dc; /* defer count */ UINT32 tncrs; /* tx - no crs count */ UINT32 sec; /* sequence err count */ UINT32 cexteer; /* carrier extension count */ UINT32 rlec; /* rx length error count */ UINT32 xonrxc; /* XON receive count */ UINT32 xontxc; /* XON transmit count */ UINT32 xoffrxc; /* XOFF receive count */ UINT32 xofftxc; /* XFF transmit count */ UINT32 fcruc; /* FC received unsupported count */ UINT32 prc64; /* packet rx (64 byte) count */ UINT32 prc127; /* packet rx (65 - 127 byte) count */ UINT32 prc255; /* packet rx (128 - 255 byte) count */ UINT32 prc511; /* packet rx (256 - 511 byte) count */ UINT32 prc1023; /* packet rx (512 - 1023 byte) count */ UINT32 prc1522; /* packet rx (1024 - 1522 byte) count */ UINT32 gprc; /* good packet received count */ UINT32 bprc; /* broadcast packet received count */ UINT32 mprc; /* Multicast packet received count */ UINT32 gptc; /* good packet transmit count */ UINT32 gorl; /* good octets receive count (low) */ UINT32 gorh; /* good octets received count (high) */ UINT32 gotl; /* good octets transmit count (lo) */ UINT32 goth; /* good octets transmit count (hi) */ UINT32 rnbc; /* receive no buffer count */ UINT32 ruc; /* receive undersize count */ UINT32 rfc; /* receive fragment count */ UINT32 roc; /* receive oversize count */ UINT32 rjc; /* receive Jabber count */ UINT32 torl; /* total octets received (lo) */ UINT32 torh; /* total octets received (hi) */ UINT32 totl; /* total octets transmit (lo) */ UINT32 toth; /* total octets transmit (hi) */ UINT32 tpr; /* total packet received */ UINT32 tpt; /* total packet transmit */ UINT32 ptc64; /* packet transmit (64 byte) count */ UINT32 ptc127; /* packet transmit (65-127 byte) count */ UINT32 ptc255; /* packet transmit (128-255 byte) count */ UINT32 ptc511; /* packet transmit (256-511 byte) count */ UINT32 ptc1023; /* packet transmit (512-1023 byte) count */ UINT32 ptc1522; /* packet transmit (1024-1522 byte) count */ UINT32 mptc; /* Multicast packet transmit count */ UINT32 bptc; /* Broadcast packet transmit count */ UINT32 tsctc; /* TCP segmentation context tx count */ UINT32 tsctfc; /* TCP segmentation context tx fail count */ UINT32 rdfh; /* rx data FIFO head */ UINT32 rdft; /* rx data FIFO tail */ UINT32 rdfhs; /* rx data FIFO head saved register */ UINT32 rdfts; /* rx data FIFO tail saved register */ UINT32 rdfpc; /* rx data FIFO packet count */ UINT32 tdfh; /* tx data FIFO head */ UINT32 tdft; /* tx data FIFO tail */ UINT32 tdfhs; /* tx data FIFO head saved register */ UINT32 tdfts; /* tx data FIFO tail saved register */ UINT32 tdfpc; /* tx data FIFO packet count */ } STA_REG;#if ((CPU_FAMILY==I960) && (defined __GNUC__))#pragma align 0 /* turn off alignment requirement */#endif /* CPU_FAMILY==I960 */#if defined(__STDC__) || defined(__cplusplus)IMPORT END_OBJ * gei82543EndLoad (char * initString);#elseIMPORT END_OBJ * gei82543EndLoad ();#endif /* defined(__STDC__) || defined(__cplusplus) */#ifdef __cplusplus}#endif#endif /* __INCGEI82543Endh */⌨️ 快捷键说明
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