gei82543end.h

IXP425的BSP代码

/* gei82543End.h - Intel 8254x network interface header */

/* Copyright 1990-2002 Wind River Systems, Inc. */
/*
modification history
--------------------
01g,28may02,jln add TX_RESTART_TRUE and TX_RESTART_NONE
01f,20apr02,jln support 82540/5/6 spr # 76739
01e,31jan02,jln change len of device name (spr#73010) 
01d,05dec01,jln add definitions for TBI compatibility workaround
01c,01oct01,jln move device ID definition to sysGei82543End.c
01b,01apr01,jln clean up after code review (partial spr#65326)
01a,08Jan01,jln written
*/

#ifndef __INCGEI82543Endh
#define __INCGEI82543Endh

/* includes */

#include "etherLib.h"
#include "miiLib.h"

#ifdef __cplusplus
extern "C" {
#endif

#if ((CPU_FAMILY==I960) && (defined __GNUC__))
#pragma align 1  /* tell gcc960 not to optimize alignments */
#endif    /* CPU_FAMILY==I960 */

/* define */

#define UNKNOWN -1
                 
#ifndef PHYS_TO_BUS_ADDR
#define PHYS_TO_BUS_ADDR(unit,physAddr)                                   \
    ((int) pDrvCtrl->adaptor.sysLocalToBus ?                                  \
    (*pDrvCtrl->adaptor.sysLocalToBus) (unit, physAddr) : physAddr)
#endif /* PHYS_TO_BUS_ADDR */

#ifndef BUS_TO_PHYS_ADDR
#define BUS_TO_PHYS_ADDR(unit,busAddr)                                     \
    ((int) pDrvCtrl->adaptor.sysBusToLocal ?                                  \
    (*pDrvCtrl->adaptor.sysBusToLocal)(unit, busAddr) : busAddr)
#endif /* BUS_TO_PHYS_ADDR */

#define TX_DESC_TYPE_CLEAN              0   /* TX descriptor type */
#define TX_DESC_TYPE_COPY               1      /* -- copy/chain/EOP */
#define TX_DESC_TYPE_CHAIN              2
#define TX_DESC_TYPE_EOP                3

/* TX descriptors structure */

#define TXDESC_BUFADRLOW_OFFSET         0   /* buf mem low offset */
#define TXDESC_BUFADRHIGH_OFFSET        4   /* buf mem high offset */
#define TXDESC_LENGTH_OFFSET            8   /* buf length offset */
#define TXDESC_CSO_OFFSET               10  /* checksum offset */
#define TXDESC_CMD_OFFSET               11  /* command offset */
#define TXDESC_STATUS_OFFSET            12  /* status offset */
#define TXDESC_CSS_OFFSET               13  /* cksum start */
#define TXDESC_SPECIAL_OFFSET           14  /* special field */
#define TXDESC_SIZE                     16  /* descriptor size */

#define TXDESC_CTX_IPCSS_OFFSET         0   /* CXT descriptor IPCSS */
#define TXDESC_CTX_TUCSS_OFFSET         4   /* CXT descriptor TUCSS */

/* RX descriptor structure */

#define RXDESC_BUFADRLOW_OFFSET         0   /* buf mem low offset */
#define RXDESC_BUFADRHIGH_OFFSET        4   /* buf mem high offset */
#define RXDESC_LENGTH_OFFSET            8   /* length offset */
#define RXDESC_CHKSUM_OFFSET            10  /* cksum offset */
#define RXDESC_STATUS_OFFSET            12  /* status offset */
#define RXDESC_ERROR_OFFSET             13  /* error offset */
#define RXDESC_SPECIAL_OFFSET           14  /* special offset */
#define RXDESC_SIZE                     16  /* descriptor size */

#define TX_ETHER_PHY_SIZE               (EH_SIZE + ETHERMTU + 2)

#define PRO1000_PCI_VENDOR_ID           0x8086 /* Intel vendor ID */
#define PRO1000_PCI_DEVICE_ID           0x1001 /* device ID */
#define PRO1000F_PCI_SUBSYSTEM_ID       0x1003 /* device subsystem ID */
#define PRO1000T_PCI_SUBSYSTEM_ID       0x1004
#define PRO1000T_PCI_DEVICE_ID          0x1004 /* bizard case */
#define PRO1000F_BOARD                  0x1003 /* backward compatible */
#define PRO1000T_BOARD                  0x1003 /* backward compatible */
#define INTEL_PCI_VENDOR_ID             0x8086

#define PRO1000_546_BOARD               0x100e /* 82540/82545/82546 MAC */
#define PRO1000_544_BOARD               0x1008 /* 82544 MAC */
#define PRO1000_543_BOARD               0x1003 /* 82543 MAC */

#define GEI_COPPER_MEDIA                1
#define GEI_FIBER_MEDIA                 2

#define GEI_PHY_GMII_TYPE               1

#define DEFAULT_RXRES_PROCESS_FACTOR    2
#define DEFAULT_TIMER_INTERVAL          2       /* 2 seconds */
#define DEFAULT_DRV_FLAGS               0
#define DEFAULT_LOAN_RXBUF_FACTOR       4
#define DEFAULT_MBLK_NUM_FACTOR         4
#define DEFAULT_MBUF_COPY_SIZE          256
#define DEFAULT_NUM_TXDES               24
#define DEFAULT_NUM_RXDES               24
#define DEFAULT_RXINT_DELAY             0
#define DEFAULT_MULTI_FILTER_TYPE       MULTI_FILTER_TYPE_47_36
#define DEFAULT_FLOW_CONTRL             FLOW_CONTRL_HW
#define DEFAULT_TX_REPORT               TX_REPORT_RS
#define DEFAULT_TIPG_IPGT_F             6
#define DEFAULT_TIPG_IPGT_T             8
#define DEFAULT_TIPG_IPGR1              8
#define DEFAULT_TIPG_IPGR2              6

#define GEI543_MAX_DEV_UNIT             4

/* flags available to config system */ 

#define GEI_END_SET_TIMER               0x0001 /* use a watchdog timer */   
#define GEI_END_SET_RX_PRIORITY         0x0002 /* RX has higher priority (543 only) */
#define GEI_END_FREE_RESOURCE_DELAY     0x0004 /* allow delay to free loaned TX cluster */ 
#define GEI_END_JUMBO_FRAME_SUPPORT     0x0008 /* Jumbo Frame allowed */
#define GEI_END_RX_IP_XSUM              0x0010 /* RX IP XSUM allowed, not supported */
#define GEI_END_RX_TCPUDP_XSUM          0x0020 /* RX TCP XSUM allowed, not supported */
#define GEI_END_TX_IP_XSUM              0x0040 /* TX IP XSUM allowed, not supported */
#define GEI_END_TX_TCPUDP_XSUM          0x0080 /* TX TCP XSUM allowed, not supported */
#define GEI_END_TX_TCP_SEGMENTATION     0x0100 /* TX TCP segmentation, not supported */
#define GEI_END_TBI_COMPATIBILITY       0x0200 /* TBI compatibility workaround (543 only) */
#define GEI_END_USER_MEM_FOR_DESC_ONLY  0x0400 /* cacheable user mem for RX descriptors only */ 

#define GEI_DEFAULT_RXDES_NUM           0x40
#define GEI_DEFAULT_TXDES_NUM           0x80
#define GEI_DEFAULT_USR_FLAG            (GEI_END_SET_TIMER | \
                                         GEI_END_SET_RX_PRIORITY | \
                                         GEI_END_FREE_RESOURCE_DELAY)

#define GEI_DEFAULT_ETHERHEADER         (SIZEOF_ETHERHEADER)
#define GEI_MAX_FRAME_SIZE              16288 /* based on default RX/TX 
                                               buffer configuration */

#define GEI_MAX_JUMBO_MTU_SIZE          (GEI_MAX_FRAME_SIZE - \
                                         GEI_DEFAULT_ETHERHEADER - \
                                         ETHER_CRC_LENGTH)   

#define GEI_DEFAULT_JUMBO_MTU_SIZE      9000      /* 9000 bytes */

#define AVAIL_TX_INT                    (INT_TXDW_BIT)
#define AVAIL_RX_INT                    (INT_RXO_BIT | INT_RXTO_BIT)
#define AVAIL_RX_TX_INT                 (AVAIL_TX_INT | AVAIL_RX_INT)
#define AVAIL_LINK_INT                  (INT_LSC_BIT)
#define INT_LINK_CHECK                  (AVAIL_LINK_INT | INT_RXCFG_BIT)
#define INTEL_82543GC_VALID_INT         (AVAIL_RX_TX_INT | INT_LINK_CHECK | INT_TXDLOW_BIT)
 
#define MAX_TXINT_DELAY                 65536
#define MAX_RXINT_DELAY                 65536
#define MIN_TXINT_DELAY                 1
#define TXINT_DELAY_LESS                5
#define TXINT_DELAY_MORE                512 

#define ETHER_CRC_LENGTH                4
#define RX_CRC_LEN                      ETHER_CRC_LENGTH
#define MAX_ETHER_PACKET_SIZE           1514 
#define MIN_ETHER_PACKET_SIZE           60
#define ETHER_ADDRESS_SIZE              6

#define CARRIER_EXTENSION_BYTE          0x0f

#define INTEL_82543GC_MTA_NUM           128

#define INTEL_82543GC_MULTIPLE_DES      8

#define TX_COLLISION_THRESHOLD          16
#define FDX_COLLISION_DISTANCE          64
#define HDX_COLLISION_DISTANCE          64
#define BIG_HDX_COLLISION_DISTANCE      512

#define NUM_RAR                         16
#define NUM_MTA                         128
#define NUM_VLAN                        128
#define MAX_NUM_MULTI                   (NUM_RAR + NUM_MTA - 1)

#define MULTI_FILTER_TYPE_47_36         0
#define MULTI_FILTER_TYPE_46_35         1
#define MULTI_FILTER_TYPE_45_34         2
#define MULTI_FILTER_TYPE_43_32         3

#define FLOW_CONTRL_NONE                0
#define FLOW_CONTRL_TRANSMIT            1
#define FLOW_CONTRL_RECEIVE             2
#define FLOW_CONTRL_ALL                 3
#define FLOW_CONTRL_HW                  0xf

#define TX_REPORT_RS                    1
#define TX_REPORT_RPS                   2

#define DMA_RX_PRIORITY                 1
#define DMA_FAIR_RX_TX                  2

#define FULL_DUPLEX_MODE                1
#define HALF_DUPLEX_MODE                2
#define DUPLEX_HW                       3
#define DEFAULT_DUPLEX_MODE             FULL_DUPLEX_MODE

#define END_SPEED_10M                   10000000    /* 10Mbs */
#define END_SPEED_100M                  100000000   /* 100Mbs */
#define END_SPEED_1000M                 1000000000  /* 1000Mbs */
#define END_SPEED                       END_SPEED_1000M

#define DEVICE_NAME                     "gei" 
#define DEVICE_NAME_LENGTH              4 

#define TYPE_PRO1000F_PCI               1
#define TYPE_PRO1000T_PCI               2
#define GEI82543_HW_AUTO                0x1
#define GEI82543_FORCE_LINK             0x2

/* general flags */

#define FLAG_POLLING_MODE               0x0001
#define FLAG_PROMISC_MODE               0x0002
#define FLAG_ALLMULTI_MODE              0x0004
#define FLAG_MULTICAST_MODE             0x0008
#define FLAG_BROADCAST_MODE             0x0010

/* misc */

#define TX_RESTART_NONE                 0x4000 /* muxTxRestart not scheduled */
#define TX_RESTART_TRUE                 0x8000 /* muxTxRestart is scheduled */
#define LINK_STATUS_OK                  0
#define LINK_STATUS_ERROR               1
#define LINK_STATUS_UNKNOWN             2
#define FREE_ALL_AUTO                   1
#define FREE_ALL_FORCE                  2
#define TX_LOAN_TRANSMIT                1
#define TX_COPY_TRANSMIT                2
#define LINK_TIMEOUT_IN_QUAR_SEC        12 /* 3s */

#define GEI_MII_PHY_CAP_FLAGS           (MII_PHY_10 | MII_PHY_100 | \
                                         MII_PHY_FD | MII_PHY_HD | \
                                         MII_PHY_1000T_FD)
/* register area */

/* TX registers */

#define INTEL_82543GC_TDBAL             0x3800  /* Tx Descriptor Base Low */
#define INTEL_82543GC_TDBAH             0x3804  /* Tx Descriptor Base High */
#define INTEL_82543GC_TDLEN             0x3808  /* Tx Descriptor Length */
#define INTEL_82543GC_TDH               0x3810  /* Tx Descriptor Head */
#define INTEL_82543GC_TDT               0x3818  /* Tx Descriptor Tail */

/* RX registers */

#define INTEL_82543GC_RDBAL             0x2800  /* Rx Descriptor Base Low */
#define INTEL_82543GC_RDBAH             0x2804  /* Rx Descriptor Base High */
#define INTEL_82543GC_RDLEN             0x2808  /* Rx Descriptor Length */
#define INTEL_82543GC_RDH               0x2810  /* Rx Descriptor Head */
#define INTEL_82543GC_RDT               0x2818  /* Rx Descriptor Tail */

/* Interrupt registers */

#define INTEL_82543GC_ICR               0xc0    /* Interrupt Cause Read */
#define INTEL_82543GC_ICS               0xc8    /* Interrupt Cause Set */
#define INTEL_82543GC_IMS               0xd0    /* Interrupt Mask Set/Read */
#define INTEL_82543GC_IMC               0xD8    /* Interrupt Mask Clear */

#define INTEL_82543GC_CTRL              0x0     /* Device Control */
#define INTEL_82543GC_STATUS            0x8	/* Device Status */
#define INTEL_82543GC_EECD              0x10    /* EEPROM/Flash Data */
#define INTEL_82543GC_CTRL_EXT          0x18    /* Extended Device Control */
#define INTEL_82543GC_MDI               0x20    /* MDI Control */
#define INTEL_82543GC_FCAL              0x28    /* Flow Control Adr Low */
#define INTEL_82543GC_FCAH              0x2c    /* Flow Control Adr High */
#define INTEL_82543GC_FCT               0x30    /* Flow Control Type */
#define INTEL_82543GC_VET               0x38    /* VLAN EtherType */