motfecend.h

IXP425的BSP代码

/* motFecEnd.h - Motorola FEC Ethernet network interface header */

/* Copyright 1990-2002 Wind River Systems, Inc. */
/* Copyright 1999-2000 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01g,01apr02,pmr  SPR 72070: passing unit number to sysFecEnetAddrGet.
01f,07dec01,rcs  added  define REV_D_3 SPR# 71420  
01e,26oct01,crg  added support for proper setting of MII management interface
                 speed (SPR 33812)
01d,21nov00,rhk  added define for revision D4 processor and for pin mux bit.
01c,11jun00,ham  removed reference to etherLib.
01b,09feb99,cn	 changes required by performance improvement (SPR# 24883).
01a,09nov98,cn	 written.
*/

#ifndef __INCmotFecEndh
#define __INCmotFecEndh

/* includes */

#ifdef __cplusplus
extern "C" {
#endif

/* defines */

/* revision D.3 and greater processors require special FEC initialization */

#define REV_D_4 0x0502
#define REV_D_3 0x0501

/*
 * redefine the macro below in the bsp if you need to access the device
 * registers/descriptors in a more suitable way.
 */

#ifndef MOT_FEC_LONG_WR
#define MOT_FEC_LONG_WR(addr, value)                                        \
    (* (addr) = ((UINT32) (value)))
#endif /* MOT_FEC_LONG_WR */

#ifndef MOT_FEC_WORD_WR
#define MOT_FEC_WORD_WR(addr, value)                                        \
    (* (addr) = ((UINT16) (value)))
#endif /* MOT_FEC_WORD_WR */

#ifndef MOT_FEC_BYTE_WR
#define MOT_FEC_BYTE_WR(addr, value)                                        \
    (* (addr) = ((UINT8) (value)))
#endif /* MOT_FEC_BYTE_WR */

#ifndef MOT_FEC_LONG_RD
#define MOT_FEC_LONG_RD(addr, value)                                        \
    ((value) = (* (UINT32 *) (addr)))
#endif /* MOT_FEC_LONG_RD */

#ifndef MOT_FEC_WORD_RD
#define MOT_FEC_WORD_RD(addr, value)                                        \
    ((value) = (* (UINT16 *) (addr)))
#endif /* MOT_FEC_WORD_RD */

#ifndef MOT_FEC_BYTE_RD
#define MOT_FEC_BYTE_RD(addr, value)                                        \
    ((value) = (* (UINT8 *) (addr)))
#endif /* MOT_FEC_BYTE_RD */

/*
 * Default macro definitions for BSP interface.
 * These macros can be redefined in a wrapper file, to generate
 * a new module with an optimized interface.
 */

#ifndef SYS_FEC_INT_CONNECT
#define SYS_FEC_INT_CONNECT(pDrvCtrl, pFunc, arg, ret)                      \
{                                                                           \
IMPORT STATUS intConnect (VOIDFUNCPTR *, VOIDFUNCPTR, int);		    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl) && (!(pDrvCtrl->intrConnect)))  		    \
    {                                                                       \
    pDrvCtrl->intrConnect = TRUE;                                   	    \
    ret = (intConnect) ((VOIDFUNCPTR*)                              	    \
                                INUM_TO_IVEC (MOT_FEC_VECTOR (pDrvCtrl)),   \
                                (pFunc), (int) (arg));                      \
    }                                                                       \
}
#endif /* SYS_FEC_INT_CONNECT */

#ifndef SYS_FEC_INT_DISCONNECT
#define SYS_FEC_INT_DISCONNECT(pDrvCtrl, pFunc, arg, ret)                   \
{                                                                           \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl) && (motFecIntDisc != NULL))             	    \
    {                                                                       \
    pDrvCtrl->intrConnect = FALSE;                                          \
    ret = (*motFecIntDisc) ((VOIDFUNCPTR*)                          	    \
                              INUM_TO_IVEC (MOT_FEC_VECTOR (pDrvCtrl)),     \
                              (pFunc));                                     \
    }                                                                       \
}
#endif /* SYS_FEC_INT_DISCONNECT */

#ifndef SYS_FEC_INT_ENABLE
#define SYS_FEC_INT_ENABLE(pDrvCtrl, ret)				    \
{                                                                           \
IMPORT int intEnable (int);						    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl)) 			    			    \
    ret = intEnable ((int) (MOT_FEC_VECTOR (pDrvCtrl)));		    \
}
#endif /* SYS_FEC_INT_ENABLE */

#ifndef SYS_FEC_INT_DISABLE
#define SYS_FEC_INT_DISABLE(pDrvCtrl, ret)				    \
{                                                                           \
IMPORT int intDisable (int);						    \
ret = OK;                                                                   \
                                                                            \
if (MOT_FEC_VECTOR (pDrvCtrl)) 			    			    \
    ret = intDisable ((int) (MOT_FEC_VECTOR (pDrvCtrl)));		    \
}
#endif /* SYS_FEC_INT_DISABLE */

#define SYS_FEC_ENET_ADDR_GET(address)                                  \
if (sysFecEnetAddrGet != NULL)                                          \
    if (sysFecEnetAddrGet (pDrvCtrl->unit, (address)) == ERROR)         \
        {                                                               \
        errnoSet (S_iosLib_INVALID_ETHERNET_ADDRESS);                   \
        return (NULL);                                                  \
        }

#define SYS_FEC_ENET_ENABLE                                             \
if (sysFecEnetEnable != NULL)                                           \
    if (sysFecEnetEnable (pDrvCtrl->motCpmAddr) == ERROR)               \
        return (ERROR);

#define SYS_FEC_ENET_DISABLE                                            \
if (sysFecEnetDisable != NULL)                                          \
    if (sysFecEnetDisable (pDrvCtrl->motCpmAddr) == ERROR)              \
        return (ERROR);

#define MOT_FEC_DEV_NAME       	"motfec"
#define MOT_FEC_DEV_NAME_LEN   	7
#define MOT_FEC_TBD_DEF_NUM    	64		/* default number of TBDs */
#define MOT_FEC_RBD_DEF_NUM    	48		/* default number of RBDs */
#define MOT_FEC_TX_CL_NUM    	6		/* number of tx clusters */
#define MOT_FEC_BD_LOAN_NUM    	32		/* loaned BDs */
#define MOT_FEC_TBD_MAX         128     	/* max number of TBDs */
#define MOT_FEC_RBD_MAX         128     	/* max number of TBDs */
#define MOT_FEC_WAIT_MAX	0xf0000000	/* max delay after sending */

#define MOT_FEC_ADDR_LEN        6               /* ethernet address length */

/* Control/Status Registers (CSR) definitions */

#define MOT_FEC_CSR_OFF         0x0e00  /* CSRs offset in the 860T RAM */
#define MOT_FEC_ADDR_L_OFF      0x0e00  /* lower 32-bits of MAC address */
#define MOT_FEC_ADDR_H_OFF      0x0e04  /* upper 16-bits of MAC address */
#define MOT_FEC_HASH_H_OFF      0x0e08  /* upper 32-bits of hash table */
#define MOT_FEC_HASH_L_OFF      0x0e0c  /* lower 32-bits of hash table */
#define MOT_FEC_RX_START_OFF    0x0e10  /* rx ring start address */
#define MOT_FEC_TX_START_OFF    0x0e14  /* tx ring start address */
#define MOT_FEC_RX_BUF_OFF      0x0e18  /* max rx buf length */
#define MOT_FEC_CTRL_OFF        0x0e40  /* FEC control register */
#define MOT_FEC_EVENT_OFF       0x0e44  /* interrupt event register */
#define MOT_FEC_MASK_OFF        0x0e48  /* interrupt mask register */
#define MOT_FEC_VEC_OFF         0x0e4c  /* interrupt level/vector register */
#define MOT_FEC_RX_ACT_OFF      0x0e50  /* rx ring has been updated */
#define MOT_FEC_TX_ACT_OFF      0x0e54  /* tx ring has been updated */
#define MOT_FEC_MII_DATA_OFF    0x0e80  /* MII data register */
#define MOT_FEC_MII_SPEED_OFF   0x0e84  /* MII speed register */
#define MOT_FEC_RX_BOUND_OFF    0x0ecc  /* rx fifo limit in the 860T ram */
#define MOT_FEC_RX_FIFO_OFF     0x0ed0  /* rx fifo base in the 860T ram */
#define MOT_FEC_TX_FIFO_OFF     0x0eec  /* tx fifo base in the 860T ram */
#define MOT_FEC_SDMA_OFF        0x0f34  /* function code to SDMA */
#define MOT_FEC_RX_CTRL_OFF     0x0f44  /* rx control register */
#define MOT_FEC_RX_FR_OFF       0x0f48  /* max rx frame length */
#define MOT_FEC_TX_CTRL_OFF     0x0f84  /* tx control register */

/* Control/Status Registers (CSR) bit definitions */

#define MOT_FEC_RX_START_MSK    0xfffffffc      /* quad-word alignment */
                                                /* required for rx BDs */

#define MOT_FEC_TX_START_MSK    0xfffffffc      /* quad-word alignment */
                                                /* required for tx BDs */
/* Ethernet CSR bit definitions */

#define MOT_FEC_ETH_PINMUX	0x00000004	/* select FEC for port D pins */
#define MOT_FEC_ETH_EN          0x00000002      /* enable Ethernet operation */
#define MOT_FEC_ETH_DIS         0x00000000      /* disable Ethernet operation */
#define MOT_FEC_ETH_RES         0x00000001      /* reset the FEC */
#define MOT_FEC_CTRL_MASK       0x00000007      /* FEC control register mask */

/*
 * interrupt bits definitions: these are common to both the
 * mask and the event register.
 */

#define MOT_FEC_EVENT_HB        0x80000000      /* heartbeat error */
#define MOT_FEC_EVENT_BABR      0x40000000      /* babbling rx error */
#define MOT_FEC_EVENT_BABT      0x20000000      /* babbling tx error */
#define MOT_FEC_EVENT_GRA       0x10000000      /* graceful stop complete */
#define MOT_FEC_EVENT_TXF       0x08000000      /* tx frame */
#define MOT_FEC_EVENT_TXB       0x04000000      /* tx buffer */
#define MOT_FEC_EVENT_RXF       0x02000000      /* rx frame */
#define MOT_FEC_EVENT_RXB       0x01000000      /* rx buffer */
#define MOT_FEC_EVENT_MII       0x00800000      /* MII transfer */
#define MOT_FEC_EVENT_BERR      0x00400000      /* U-bus access error */
#define MOT_FEC_EVENT_MSK       0xffc00000      /* clear all interrupts */
#define MOT_FEC_MASK_ALL        MOT_FEC_EVENT_MSK    /* mask all interrupts */

/* bit masks for the interrupt level/vector CSR */

#define MOT_FEC_LVL_MSK         0xe0000000      /* intr level */
#define MOT_FEC_TYPE_MSK        0x0000000c      /* highest pending intr */
#define MOT_FEC_VEC_MSK         0xe000000c      /* this register mask */
#define MOT_FEC_RES_MSK         0x1ffffff3      /* reserved bits */
#define MOT_FEC_LVL_SHIFT       0x1d            /* intr level bits location */

/* transmit and receive active registers definitions */

#define MOT_FEC_TX_ACT          0x01000000      /* tx active bit */
#define MOT_FEC_RX_ACT          0x01000000      /* rx active bit */

/* MII management frame CSRs */

#define MOT_FEC_MII_ST          0x40000000      /* start of frame delimiter */
#define MOT_FEC_MII_OP_RD       0x20000000      /* perform a read operation */
#define MOT_FEC_MII_OP_WR       0x10000000      /* perform a write operation */
#define MOT_FEC_MII_ADDR_MSK    0x0f800000      /* PHY address field mask */
#define MOT_FEC_MII_REG_MSK     0x007c0000      /* PHY register field mask */
#define MOT_FEC_MII_TA          0x00020000      /* turnaround */
#define MOT_FEC_MII_DATA_MSK    0x0000ffff      /* PHY data field */
#define MOT_FEC_MII_RA_SHIFT    0x12            /* mii reg address bits */
#define MOT_FEC_MII_PA_SHIFT    0x17            /* mii PHY address bits */

#define MOT_FEC_MII_PRE_DIS     0x00000080      /* desable preamble */
#define MOT_FEC_MII_SPEED_25    0x00000005      /* recommended for 25Mhz CPU */
#define MOT_FEC_MII_SPEED_33    0x00000007      /* recommended for 33Mhz CPU */
#define MOT_FEC_MII_SPEED_40    0x00000008      /* recommended for 40Mhz CPU */
#define MOT_FEC_MII_SPEED_50    0x0000000a      /* recommended for 50Mhz CPU */
#define MOT_FEC_MII_SPEED_SHIFT	1		/* MII_SPEED bits location */
#define MOT_FEC_MII_CLOCK_MAX	2500000		/* max freq of MII clock (Hz) */
#define MOT_FEC_MII_MAN_DIS     0x00000000      /* disable the MII management */
                                                /* interface */
#define MOT_FEC_MII_SPEED_MSK   0xffffff81      /* speed field mask */

/* FIFO transmit and receive CSRs definitions */

#define MOT_FEC_FIFO_MSK        0x000003ff      /* FIFO rx/tx/bound mask */

/* SDMA function code CSR */

#define MOT_FEC_SDMA_DATA_BE    0x60000000      /* big-endian byte-ordering */
                                                /* for SDMA data transfer */

#define MOT_FEC_SDMA_DATA_PPC   0x20000000      /* PPC byte-ordering */
                                                /* for SDMA data transfer */

#define MOT_FEC_SDMA_DATA_RES   0x00000000      /* reserved value */

#define MOT_FEC_SDMA_BD_BE      0x18000000      /* big-endian byte-ordering */
                                                /* for SDMA BDs transfer */

#define MOT_FEC_SDMA_BD_PPC     0x08000000      /* PPC byte-ordering */
                                                /* for SDMA BDs transfer */


#define MOT_FEC_SDMA_BD_RES     0x00000000      /* reserved value */
#define MOT_FEC_SDMA_FUNC_0     0x00000000      /* no function code */

/* receive control/hash registers bit definitions */

#define MOT_FEC_RX_CTRL_PROM    0x00000008      /* promiscous mode */
#define MOT_FEC_RX_CTRL_MII     0x00000004      /* select MII interface */
#define MOT_FEC_RX_CTRL_DRT     0x00000002      /* disable rx on transmit */
#define MOT_FEC_RX_CTRL_LOOP    0x00000001      /* loopback mode */
#define MOT_FEC_RX_FR_MSK       0x000007ff      /* rx frame length mask */


/* transmit control register bit definitions */

#define MOT_FEC_TX_CTRL_FD      0x00000004      /* enable full duplex mode */
#define MOT_FEC_TX_CTRL_HBC     0x00000002      /* HB check is performed */
#define MOT_FEC_TX_CTRL_GRA     0x00000001      /* issue a graceful tx stop */

/* rx/tx buffer descriptors definitions */

#define MOT_FEC_RBD_SZ          8       /* RBD size in byte */
#define MOT_FEC_TBD_SZ          8       /* TBD size in byte */
#define MOT_FEC_TBD_MIN         6       /* min number of TBDs */
#define MOT_FEC_RBD_MIN         4       /* min number of RBDs */
#define MOT_FEC_TBD_POLL_NUM    1       /* one TBD for poll operation */
#define CL_OVERHEAD             4       /* prepended cluster overhead */
#define CL_ALIGNMENT            4       /* cluster required alignment */
#define MBLK_ALIGNMENT          4       /* mBlks required alignment */
#define MOT_FEC_BD_ALIGN        0x10    /* required alignment for RBDs */
#define MOT_FEC_MAX_PCK_SZ      (ETHERMTU + SIZEOF_ETHERHEADER          \
                                 + ETHER_CRC_LEN)

#define MOT_FEC_BD_STAT_OFF     0       /* offset of the status word */
#define MOT_FEC_BD_LEN_OFF      2       /* offset of the data length word */
#define MOT_FEC_BD_ADDR_OFF     4       /* offset of the data pointer word */

/* TBD bits definitions */

#define MOT_FEC_TBD_RDY         0x8000          /* ready for transmission */
#define MOT_FEC_TBD_TO1         0x4000          /* transmit ownership bit 1 */
#define MOT_FEC_TBD_WRAP        0x2000          /* look at CSR5 for next bd */