m8260fcc.h

IXP425的BSP代码

						/* 1518 bytes */
#define M8260_FCC_JBRC_OFF	0xDC		/* bad packets longer than */
						/* 1518 bytes */
#define M8260_FCC_P64C_OFF	0xE0		/* packets 64-byte long */
#define M8260_FCC_P65C_OFF	0xE4		/* packets < 128 bytes and */
						/* > 64 bytes */
#define M8260_FCC_P128C_OFF	0xE8		/* packets < 256 bytes and */ 
						/* > 127 bytes */
#define M8260_FCC_P256C_OFF	0xEC		/* packets < 512 bytes and */ 
						/* > 255 bytes */
#define M8260_FCC_P512C_OFF	0xF0		/* packets < 1024 bytes and */ 
						/* > 511 bytes */
#define M8260_FCC_P1024C_OFF	0xF4		/* packets < 1519 bytes and */ 
						/* > 1023 bytes */
#define M8260_FCC_CAM_BUF_OFF	0xF8		/* internal buffer */
#define M8260_FCC_RES3_OFF	0xFC		/* reserved */

/* General FCC Mode Register definitions */
 
#define M8260_GFMR_HDLC		0x00000000      /* HDLC mode */
#define M8260_GFMR_RES1		0x00000001      /* reserved mode */
#define M8260_GFMR_RES2		0x00000002      /* reserved mode */
#define M8260_GFMR_RES3		0x00000003      /* reserved mode */
#define M8260_GFMR_RES4		0x00000004      /* reserved mode */
#define M8260_GFMR_RES5		0x00000005      /* reserved mode */
#define M8260_GFMR_RES6		0x00000006      /* reserved mode */
#define M8260_GFMR_RES7		0x00000007      /* reserved mode */
#define M8260_GFMR_RES8		0x00000008      /* reserved mode */
#define M8260_GFMR_RES9		0x00000009      /* reserved mode */
#define M8260_GFMR_ATM		0x0000000a      /* ATM mode */
#define M8260_GFMR_RES10	0x0000000b      /* reserved mode */
#define M8260_GFMR_ETHERNET	0x0000000c      /* ethernet mode */
#define M8260_GFMR_RES11	0x0000000d      /* reserved mode */
#define M8260_GFMR_RES12	0x0000000e      /* reserved mode */
#define M8260_GFMR_RES13	0x0000000f      /* reserved mode */
#define M8260_GFMR_NORM		0x00000000      /* normal mode */
#define M8260_GFMR_LOOP		0x40000000      /* local loopback */
#define M8260_GFMR_ECHO		0x80000000      /* automatic echo */
#define M8260_GFMR_LOOP_ECHO	0xc0000000      /* loop & echo */
#define M8260_GFMR_TCI       	0x20000000      /* tx clock invert */
#define M8260_GFMR_TRX        	0x10000000      /* transparent receiver */
#define M8260_GFMR_TTX       	0x08000000      /* transparent transmitter */
#define M8260_GFMR_CDP        	0x04000000      /* CD* pulse */
#define M8260_GFMR_CTSP       	0x02000000      /* CTS* pulse */
#define M8260_GFMR_CDS        	0x01000000      /* CD* sampling */
#define M8260_GFMR_CTSS       	0x00800000      /* CTS* sampling */
#define M8260_GFMR_SYN_EXT    	0x00000000      /* external sync */
#define M8260_GFMR_SYN_AUTO   	0x00004000      /* automatic sync */
#define M8260_GFMR_SYN_8	0x00008000      /* 8-bit sync pattern */
#define M8260_GFMR_SYN_16	0x0000c000      /* 16-bit sync pattern */
#define M8260_GFMR_RTSM		0x00002000      /* RTS* mode */
#define M8260_GFMR_RENC_RES   	0x00001000      /* receiver encoding reserved */
#define M8260_GFMR_RENC_NRZI  	0x00000800      /* receiver encoding NRZI */
#define M8260_GFMR_RENC_NRZ   	0x00000000      /* receiver encoding NRZ */
#define M8260_GFMR_REVD       	0x00000400      /* reverse data */
#define M8260_GFMR_TENC_RES   	0x00000200      /* transmitter encoding res */
#define M8260_GFMR_TENC_NRZI  	0x00000100      /* transmitter encoding NRZI */
#define M8260_GFMR_TENC_NRZ   	0x00000000      /* transmitter encoding NRZ */
#define M8260_GFMR_TCRC_RES   	0x00000040      /* transparent CRC reserved */
#define M8260_GFMR_TCRC_16    	0x00000000      /* 16-bit transparent CRC */
#define M8260_GFMR_TCRC_32    	0x00000080      /* 32-bit transparent CRC */
#define M8260_GFMR_ENT		0x00000010      /* enable transmitter */
#define M8260_GFMR_ENR		0x00000020      /* enable receiver */

/* FCC Data Synchronization Register definitions */
 
#define M8260_FDSR_SYN1_MASK	0x00ff      	/* sync pattern mask 1 */
#define M8260_FDSR_SYN2_MASK	0xff00      	/* sync pattern mask 2 */
#define M8260_FDSR_ETH_SYN1	0x55      	/* Ethernet sync pattern 1 */
#define M8260_FDSR_ETH_SYN2	0xd5      	/* Ethernet sync pattern 2 */

/* FCC Transmit on Demand Register definitions */
 
#define M8260_FTODR_TOD		0x8000      	/* transmit on demand */

/* FCC Function Code Register definitions */
 
#define M8260_FCR_GBL		0x20      	/* global mem operation */
						/* enable snooping */
#define M8260_FCR_BO_BE		0x10      	/* big-endian ordering */
#define M8260_FCR_BO_LE		0x08      	/* little-endian ordering */
#define M8260_FCR_TC2		0x04      	/* transfer code for TC[2] */
#define M8260_FCR_DTB		0x02      	/* data is in the local bus */
#define M8260_FCR_BDB		0x01      	/* BDs are in the local bus */
#define M8260_FCR_SHIFT		24      	/* get to fcr bits in xstate */

/* FCC Ethernet Protocol Specific Mode Register definitions */
 
#define M8260_FPSMR_ETH_HBC	0x80000000          /* heartbeat checking */
#define M8260_FPSMR_ETH_FC	0x40000000          /* force collision */
#define M8260_FPSMR_ETH_SBT	0x20000000          /* stop backoff timer */
#define M8260_FPSMR_ETH_LPB	0x10000000          /* loopback operation */
#define M8260_FPSMR_ETH_LCW	0x08000000          /* late collision window */
#define M8260_FPSMR_ETH_FDE	0x04000000          /* full duplex enable */
#define M8260_FPSMR_ETH_MON	0x02000000          /* enable RMON mode */
#define M8260_FPSMR_ETH_PRO	0x00400000          /* enable promiscous mode */
#define M8260_FPSMR_ETH_FCE	0x00200000          /* flow control enable */
#define M8260_FPSMR_ETH_RSH	0x00100000          /* receive short frame */
#define M8260_FPSMR_ETH_CAM	0x00000400          /* CAM address matching */
#define M8260_FPSMR_ETH_BRO	0x00000200          /* broadcast enable */
#define M8260_FPSMR_ETH_CRC_32	0x00000080          /* use 32-bit CCITT CRC */
#define M8260_FPSMR_ETH_CRC_MASK	0x000000c0          /* CRC mask field */

/* FCC Ethernet Event and Mask Register definitions */
 
#define M8260_FEM_ETH_RES      0xff00          /* reserved mask */
#define M8260_FEM_ETH_EVENT    0x00ff          /* event mask */
#define M8260_FEM_ETH_GRA      0x0080          /* graceful stop event */
#define M8260_FEM_ETH_RXC      0x0040          /* rx control frame event */
#define M8260_FEM_ETH_TXC      0x0020          /* tx control frame event */
#define M8260_FEM_ETH_TXE      0x0010          /* transmission error event */
#define M8260_FEM_ETH_RXF      0x0008          /* frame received event */
#define M8260_FEM_ETH_BSY      0x0004          /* busy condition */
#define M8260_FEM_ETH_TXB      0x0002          /* buffer transmitted event */
#define M8260_FEM_ETH_RXB      0x0001          /* buffer received event */
 
/* FCC Ethernet Receive Buffer Descriptor definitions */
 
#define M8260_FETH_RBD_E       0x8000          /* buffer is empty */
#define M8260_FETH_RBD_W       0x2000          /* last BD in ring */
#define M8260_FETH_RBD_I       0x1000          /* interrupt on receive */
#define M8260_FETH_RBD_L       0x0800          /* buffer is last in frame */
#define M8260_FETH_RBD_F       0x0400          /* buffer is first in frame */
#define M8260_FETH_RBD_M       0x0100          /* miss bit for prom mode */
#define M8260_FETH_RBD_BC      0x0080          /* broadcast address frame */
#define M8260_FETH_RBD_MC      0x0040          /* multicast address frame */
#define M8260_FETH_RBD_LG      0x0020          /* frame length violation */
#define M8260_FETH_RBD_NO      0x0010          /* nonoctet aligned frame */
#define M8260_FETH_RBD_SH      0x0008          /* short frame received */
#define M8260_FETH_RBD_CR      0x0004          /* Rx CRC error */
#define M8260_FETH_RBD_OV      0x0002          /* overrun condition */
#define M8260_FETH_RBD_CL      0x0001          /* collision condition */
 
/* FCC Ethernet Transmit Buffer Descriptor definitions */
 
#define M8260_FETH_TBD_R       0x8000          /* buffer is ready */
#define M8260_FETH_TBD_PAD     0x4000          /* auto pad short frames */
#define M8260_FETH_TBD_W       0x2000          /* last BD in ring */
#define M8260_FETH_TBD_I       0x1000          /* interrupt on transmit */
#define M8260_FETH_TBD_L       0x0800          /* buffer is last in frame */
#define M8260_FETH_TBD_TC      0x0400          /* auto transmit CRC */
#define M8260_FETH_TBD_DEF     0x0200          /* defer indication */
#define M8260_FETH_TBD_HB      0x0100          /* heartbeat */
#define M8260_FETH_TBD_LC      0x0080          /* late collision */
#define M8260_FETH_TBD_RL      0x0040          /* retransmission limit */
#define M8260_FETH_TBD_RC      0x003c          /* retry count */
#define M8260_FETH_TBD_UN      0x0002          /* underrun */
#define M8260_FETH_TBD_CSL     0x0001          /* carrier sense lost */
 
#ifdef __cplusplus
}
#endif

#endif /* __INCm8260Fcch */