m8260fcc.h

IXP425的BSP代码

/* m8260Fcc.h - Motorola MPC8260 Fast Communications Controller header file */

/* Copyright 1984-1999 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,12sep99,ms_  created from m8260Cpm.h, 01d.
*/

/*
 * This file contains constants for the Fast Communications Controllers
 * (fCCs) in the Motorola MPC8260 PowerQUICC II integrated Communications
 * Processor
 */

#ifndef __INCm8260Fcch
#define __INCm8260Fcch

#ifdef __cplusplus
extern "C" {
#endif

#ifndef M8260ABBREVIATIONS
#define M8260ABBREVIATIONS

#ifdef  _ASMLANGUAGE
#define CAST(x)
#else /* _ASMLANGUAGE */
typedef volatile UCHAR VCHAR;   /* shorthand for volatile UCHAR */
typedef volatile INT32 VINT32; /* volatile unsigned word */
typedef volatile INT16 VINT16; /* volatile unsigned halfword */
typedef volatile INT8 VINT8;   /* volatile unsigned byte */
typedef volatile UINT32 VUINT32; /* volatile unsigned word */
typedef volatile UINT16 VUINT16; /* volatile unsigned halfword */
typedef volatile UINT8 VUINT8;   /* volatile unsigned byte */
#define CAST(x) (x)
#endif  /* _ASMLANGUAGE */

#endif /* M8260ABBREVIATIONS */

/*
 * MPC8260 internal register/memory map (section 17 of prelim. spec)
 * note that these are offsets from the value stored in the IMMR
 * register. Also note that in the MPC8260, the IMMR is not a special
 * purpose register, but it is memory mapped.
 */
 
/* CPM mux FCC clock route register */

#define M8260_CMXFCR(base)   (CAST(VUINT32 *)((base) + 0x11B04)) 

/* FCC 1 register set */
 
#define M8260_FGMR1(base)   (CAST(VUINT32 *)((base) + 0x11300)) /* Gen Mode */
#define M8260_FPSMR1(base)  (CAST(VUINT32 *)((base) + 0x11304)) /* Prot Spec */
#define M8260_FTODR1(base)  (CAST(VUINT32 *)((base) + 0x11308)) /* transmit */
								/* on demand */
#define M8260_FDSR1(base)   (CAST(VUINT32 *)((base) + 0x1130C)) /* data sync */
#define M8260_FCCER1(base)  (CAST(VUINT32 *)((base) + 0x11310)) /* event */
#define M8260_FCCMR1(base)  (CAST(VUINT32 *)((base) + 0x11304)) /* mask */
#define M8260_FCCSR1(base)  (CAST(VUINT32 *)((base) + 0x11308)) /* status */

/* FCC1 transmit internal rate registers for PHY 0-3 */

#define M8260_FTIRR1_PHY0(base)	(CAST(VUINT32 *)((base) + 0x1131C)) 
#define M8260_FTIRR1_PHY1(base)	(CAST(VUINT32 *)((base) + 0x1131D)) 
#define M8260_FTIRR1_PHY2(base)	(CAST(VUINT32 *)((base) + 0x1131E)) 
#define M8260_FTIRR1_PHY3(base)	(CAST(VUINT32 *)((base) + 0x1131F)) 

/* offsets in internal RAM of FCC registers */

#define M8260_FCC_IRAM_GAP	0x20		/* gap between FCCs */
						/* in Internal RAM */
#define M8260_FCC_GFMR_OFF	0x0		/* GFMR offset */
#define M8260_FCC_FPSMR_OFF	0x4		/* FPSMR offset */
#define M8260_FCC_FTODR_OFF	0x8		/* FTODR offset */
#define M8260_FCC_FDSR_OFF	0xC		/* FDSR offset */
#define M8260_FCC_FCCER_OFF	0x10		/* FCCER offset */
#define M8260_FCC_FCCMR_OFF	0x14		/* FCCMR offset */
#define M8260_FCC_FCCSR_OFF	0x18		/* FCCSR offset */

/* FCC Dual-Ported RAM definitions */
 
#define M8260_FCC1_BASE(base)	(CAST(VUINT32 *)((base) + 0x8400)) /* FCC1 */
#define M8260_FCC2_BASE(base)	(CAST(VUINT32 *)((base) + 0x8500)) /* FCC2 */
#define M8260_FCC3_BASE(base)	(CAST(VUINT32 *)((base) + 0x8600)) /* FCC3 */
#define M8260_FCC_DPRAM_GAP	0x100		/* gap between FCCs */
						/* parameter RAM in DPRAM */
#define M8260_FCC_RIPTR_OFF	0x0		/* rx FIFO pointer offset */
#define M8260_FCC_TIPTR_OFF	0x2		/* tx FIFO pointer offset */
#define M8260_FCC_RES1_OFF	0x4		/* reserved */
#define M8260_FCC_MRBLR_OFF	0x6		/* max rx buffer length */
#define M8260_FCC_RSTATE_OFF	0x8		/* rx internal state */
#define M8260_FCC_RBASE_OFF	0xC		/* RBD base address */
#define M8260_FCC_RBDSTAT_OFF	0x10		/* RBD status/control */
#define M8260_FCC_RBDLEN_OFF	0x12		/* RBD data length */
#define M8260_FCC_RDPTR_OFF	0x14		/* RBD data pointer */
#define M8260_FCC_TSTATE_OFF	0x18		/* tx internal state */
#define M8260_FCC_TBASE_OFF	0x1C		/* TBD base address */
#define M8260_FCC_TBDSTAT_OFF	0x20		/* TBD status/control */
#define M8260_FCC_TBDLEN_OFF	0x22		/* TBD data length */
#define M8260_FCC_TDPTR_OFF	0x24		/* TBD data pointer */
#define M8260_FCC_RBPTR_OFF	0x28		/* RBD pointer */
#define M8260_FCC_TBPTR_OFF	0x2C		/* TBD pointer */
#define M8260_FCC_RCRC_OFF	0x30		/* temp rx CRC */
#define M8260_FCC_TCRC_OFF	0x34		/* temp tx CRC */

#define M8260_FCC_STATBUF_OFF	0x3C		/* internal buffer */
#define M8260_FCC_CAM_PTR_OFF	0x40		/* CAM address */
#define M8260_FCC_C_MASK_OFF	0x44		/* MASK for CRC */
#define M8260_FCC_C_PRES_OFF	0x48		/* preset CRC */
#define M8260_FCC_CRCEC_OFF	0x4C		/* CRC error counter */
#define M8260_FCC_ALEC_OFF	0x50		/* alignment error counter */
#define M8260_FCC_DISFC_OFF	0x54		/* discard frame counter */
#define M8260_FCC_RET_LIM_OFF	0x58		/* retry limit */
#define M8260_FCC_RET_CNT_OFF	0x5A		/* retry limit counter */
#define M8260_FCC_P_PER_OFF	0x5C		/* persistence */
#define M8260_FCC_BOFF_CNT_OFF	0x5E		/* backoff counter */
#define M8260_FCC_GADDR_H_OFF	0x60		/* group address filter high */
#define M8260_FCC_GADDR_L_OFF	0x64		/* group address filter low */
#define M8260_FCC_TFCSTAT_OFF	0x68		/* out-of-sequence TBD stat */
#define M8260_FCC_TFCLEN_OFF	0x6A		/* out-of-sequence TBD length */
#define M8260_FCC_TFCPTR_OFF	0x6C		/* out-of-sequence TBD pointer*/
#define M8260_FCC_MFLR_OFF	0x70		/* max receive frame length */
#define M8260_FCC_PADDR_H_OFF	0x72		/* individual address high */
#define M8260_FCC_PADDR_M_OFF	0x74		/* individual address medium */
#define M8260_FCC_PADDR_L_OFF	0x76		/* individual address low */
#define M8260_FCC_IBD_CNT_OFF	0x78		/* internal BD counter */
#define M8260_FCC_IBD_START_OFF	0x7A		/* internal BD start pointer */
#define M8260_FCC_IBD_END_OFF	0x7C		/* internal BD end pointer */
#define M8260_FCC_TX_LEN_OFF	0x7E		/* tx frame length counter */
#define M8260_FCC_IBD_BASE_OFF	0x80		/* internal BD base */
#define M8260_FCC_IADDR_H_OFF	0xA0		/* individual addr filter high*/
#define M8260_FCC_IADDR_L_OFF	0xA4		/* individual addr filter low */
#define M8260_FCC_MINFLR_OFF	0xA8		/* min frame lenght */
#define M8260_FCC_TADDR_H_OFF	0xAA		/* set hash table addr high */
#define M8260_FCC_TADDR_M_OFF	0xAC		/* set hash table addr medium */
#define M8260_FCC_TADDR_L_OFF	0xAE		/* set hash table addr low */
#define M8260_FCC_PAD_PTR_OFF	0xB0		/* internal PAD pointer */
#define M8260_FCC_RES2_OFF	0xB2		/* reserved */
#define M8260_FCC_CF_RANGE_OFF	0xB4		/* control frame range */
#define M8260_FCC_MAX_B_OFF	0xB6		/* max BD byte counter */
#define M8260_FCC_MAXD1_OFF	0xB8		/* max DMA1 lenght */
#define M8260_FCC_MAXD2_OFF	0xBA		/* max DMA2 lenght */
#define M8260_FCC_MAXD_OFF	0xBC		/* rx max DMA lenght */
#define M8260_FCC_DMA_CNT_OFF	0xBE		/* rx DMA counter */
#define M8260_FCC_OCTC_OFF	0xC0		/* data octets number */
#define M8260_FCC_COLC_OFF	0xC4		/* collision estimate */
#define M8260_FCC_BROC_OFF	0xC8		/* received broadast packets */
#define M8260_FCC_MULC_OFF	0xCC		/* received multicast packets */
#define M8260_FCC_USPC_OFF	0xD0		/* good packets shorter than */
						/* 64 bytes */
#define M8260_FCC_FRGC_OFF	0xD4		/* bad packets shorter than */
						/* 64 bytes */
#define M8260_FCC_OSPC_OFF	0xD8		/* good packets longer than */