mpc107meminit.h

IXP425的BSP代码

#define MPC107_BANK5_ADRS	(MPC107_BANK4_ADRS + MPC107_BANK4_SIZE)
#define MPC107_BANK6_ADRS	(MPC107_BANK5_ADRS + MPC107_BANK5_SIZE)
#define MPC107_BANK7_ADRS	(MPC107_BANK6_ADRS + MPC107_BANK6_SIZE)
#define MPC107_BANK7_ADRS_END	((MPC107_BANK7_ADRS + MPC107_BANK7_SIZE) - 1)

/* setup which memory banks to enable */

#define MPC107_MBER_DEFAULT	MPC107_BANK0_ENABLE_DATA | \
                                MPC107_BANK1_ENABLE_DATA | \
                                MPC107_BANK2_ENABLE_DATA | \
                                MPC107_BANK3_ENABLE_DATA | \
                                MPC107_BANK4_ENABLE_DATA | \
                                MPC107_BANK5_ENABLE_DATA | \
                                MPC107_BANK6_ENABLE_DATA | \
                                MPC107_BANK7_ENABLE_DATA

/* break down the mapping addresses into MPC107 register settings */

#define MPC107_START_BANK0	(((MPC107_BANK0_ADRS)     >> 20) & (0x3ff))
#define MPC107_ENDOF_BANK0	(((MPC107_BANK1_ADRS - 1) >> 20) & (0x3ff))
#define MPC107_START_BANK1	(((MPC107_BANK1_ADRS)     >> 20) & (0x3ff))
#define MPC107_ENDOF_BANK1	(((MPC107_BANK2_ADRS - 1) >> 20) & (0x3ff))
#define MPC107_START_BANK2	(((MPC107_BANK2_ADRS)     >> 20) & (0x3ff))
#define MPC107_ENDOF_BANK2	(((MPC107_BANK3_ADRS - 1) >> 20) & (0x3ff))
#define MPC107_START_BANK3	(((MPC107_BANK3_ADRS)     >> 20) & (0x3ff))
#define MPC107_ENDOF_BANK3	(((MPC107_BANK4_ADRS - 1) >> 20) & (0x3ff))
#define MPC107_START_BANK4	(((MPC107_BANK4_ADRS)     >> 20) & (0x3ff))
#define MPC107_ENDOF_BANK4	(((MPC107_BANK5_ADRS - 1) >> 20) & (0x3ff))
#define MPC107_START_BANK5	(((MPC107_BANK5_ADRS)     >> 20) & (0x3ff))
#define MPC107_ENDOF_BANK5	(((MPC107_BANK6_ADRS - 1) >> 20) & (0x3ff))
#define MPC107_START_BANK6	(((MPC107_BANK6_ADRS)     >> 20) & (0x3ff))
#define MPC107_ENDOF_BANK6	(((MPC107_BANK7_ADRS - 1) >> 20) & (0x3ff))
#define MPC107_START_BANK7	(((MPC107_BANK7_ADRS)     >> 20) & (0x3ff))
#define MPC107_ENDOF_BANK7	(((MPC107_BANK7_ADRS_END) >> 20) & (0x3ff))

#define STMEM_MASK 		(0x0ff)	/* Start of Memory Mask */
#define XTMEM_MASK 		(0x003) /* Extended Memory Mask */

/* Setup the actual MPC107 register values.*/

/* memory starting address register one */

#define MPC107_MSAR1_DEFAULT	(((MPC107_START_BANK0 & STMEM_MASK) << 0)  | \
			 ((MPC107_START_BANK1 & STMEM_MASK) << 8)  | \
			 ((MPC107_START_BANK2 & STMEM_MASK) << 16) | \
			 ((MPC107_START_BANK3 & STMEM_MASK) << 24))

/* memory starting extended address register one */

#define MPC107_XMSAR1_DEFAULT ((((MPC107_START_BANK0 >> 8) & XTMEM_MASK) << 0) \
			 | (((MPC107_START_BANK1 >> 8) & XTMEM_MASK) << 8)   \
			 | (((MPC107_START_BANK2 >> 8) & XTMEM_MASK) << 16)  \
			 | (((MPC107_START_BANK3 >> 8) & XTMEM_MASK) << 24))

/* memory ending address register one */

#define MPC107_MEAR1_DEFAULT	(((MPC107_ENDOF_BANK0 & STMEM_MASK) << 0)  | \
			 ((MPC107_ENDOF_BANK1 & STMEM_MASK) << 8)  | \
			 ((MPC107_ENDOF_BANK2 & STMEM_MASK) << 16) | \
			 ((MPC107_ENDOF_BANK3 & STMEM_MASK) << 24))

/* memory ending extended address register one */

#define MPC107_XMEAR1_DEFAULT ((((MPC107_ENDOF_BANK0 >> 8) & XTMEM_MASK) << 0) \
			 | (((MPC107_ENDOF_BANK1 >> 8) & XTMEM_MASK) << 8)   \
			 | (((MPC107_ENDOF_BANK2 >> 8) & XTMEM_MASK) << 16)  \
			 | (((MPC107_ENDOF_BANK3 >> 8) & XTMEM_MASK) << 24))

/* memory starting address register two */

#define MPC107_MSAR2_DEFAULT 	(((MPC107_START_BANK4 & STMEM_MASK) << 0)  | \
                         ((MPC107_START_BANK5 & STMEM_MASK) << 8)  | \
			 ((MPC107_START_BANK6 & STMEM_MASK) << 16) | \
			 ((MPC107_START_BANK7 & STMEM_MASK) << 24))

/* memory starting extended address register two */

#define MPC107_XMSAR2_DEFAULT ((((MPC107_START_BANK4 >> 8) & XTMEM_MASK) << 0) \
			 | (((MPC107_START_BANK5 >> 8) & XTMEM_MASK) << 8)   \
			 | (((MPC107_START_BANK6 >> 8) & XTMEM_MASK) << 16)  \
			 | (((MPC107_START_BANK7 >> 8) & XTMEM_MASK) << 24))

/* memory ending address register two */

#define MPC107_MEAR2_DEFAULT	(((MPC107_ENDOF_BANK4 & STMEM_MASK) <<  0) | \
			 ((MPC107_ENDOF_BANK5 & STMEM_MASK) <<  8) | \
			 ((MPC107_ENDOF_BANK6 & STMEM_MASK) << 16) | \
			 ((MPC107_ENDOF_BANK7 & STMEM_MASK) << 24))

/* memory ending extended address register two */

#define MPC107_XMEAR2_DEFAULT ((((MPC107_ENDOF_BANK4 >> 8) & XTMEM_MASK) << 0) \
			 | (((MPC107_ENDOF_BANK5 >> 8) & XTMEM_MASK) <<  8)  \
			 | (((MPC107_ENDOF_BANK6 >> 8) & XTMEM_MASK) << 16)  \
			 | (((MPC107_ENDOF_BANK7 >> 8) & XTMEM_MASK) << 24))

/*
 * initial values for the MPC107 SDRAM memory control registers.
 * Refer to MPC107 users manual and addendums for details on values.
 * These defaults are to support SDRAM
 */

/*  The Memory control Configuration  Register - 1  (MCCR1) */

#define MPC107_MCCR1_DEFAULT	 (MPC107_MCC1_ROMNAL_DATA << \
                                  MPC107_MCC1_ROMNAL_SHIFT) | \
                                 (MPC107_MCC1_ROMFAL_DATA << \
                                  MPC107_MCC1_ROMFAL_SHIFT) | \
                                  MPC107_MCC1_BANK7_ROWS_DATA | \
                                  MPC107_MCC1_BANK6_ROWS_DATA | \
                                  MPC107_MCC1_BANK5_ROWS_DATA | \
                                  MPC107_MCC1_BANK4_ROWS_DATA | \
                                  MPC107_MCC1_BANK3_ROWS_DATA | \
                                  MPC107_MCC1_BANK2_ROWS_DATA | \
                                  MPC107_MCC1_BANK1_ROWS_DATA | \
                                  MPC107_MCC1_BANK0_ROWS_DATA |\
                                ((MPC107_MCC1_BURST_DATA << \
                                  MPC107_MCC1_BURST_SHIFT) & \
                                  MPC107_MCC1_BURST_MASK)



/*  The Memory control Configuration  Register - 2  (MCCR2) */

#define MPC107_MCCR2_DEFAULT	  ((MPC107_MCC2_REFINT_DATA << \
                                    MPC107_MCC2_REFINT_SHIFT) & \
                                    MPC107_MCC2_REFINT_MASK) | \
                                  ((MPC107_MCC2_TS_WAIT_TIMER_DATA << \
                                    MPC107_MCC2_TS_WAIT_TIMER_S) & \
                                    MPC107_MCC2_TS_WAIT_TIMER_M) | \
                                  ((MPC107_MCC2_ASRISE_DATA << \
                                    MPC107_MCC2_ASRISE_SHIFT) &\
                                    MPC107_MCC2_ASRISE_MASK) | \
                                  ((MPC107_MCC2_ASFALL_DATA << \
                                    MPC107_MCC2_ASFALL_SHIFT) & \
                                    MPC107_MCC2_ASFALL_MASK) | \
                                    MPC107_MCC2_EDO_DATA | \
                                  ((MPC107_MCC2_ECCEN_DATA << \
                                    MPC107_MCC2_ECCEN_SHIFT) & \
                                    MPC107_MCC2_ECCEN_MASK) | \
                                  ((MPC107_MCC2_PAR_OR_ECC_D <<\
                                    MPC107_MCC2_PAR_OR_ECC_S) &\
                                    MPC107_MCC2_PAR_OR_ECC_M) | \
                                  ((MPC107_MCC2_WR_PAR_CHK_D << \
                                    MPC107_MCC2_WR_PAR_CHK_S) & \
                                    MPC107_MCC2_WR_PAR_CHK_M) |\
                                  ((MPC107_MCC2_RD_PARECC_D << \
                                    MPC107_MCC2_RD_PARECC_S) & \
                                    MPC107_MCC2_RD_PARECC_M) | \
                                  ((MPC107_MCC2_RSV_PG_DATA << \
                                    MPC107_MCC2_RSV_PG_SHIFT) & \
                                    MPC107_MCC2_RSV_PG_MASK)| \
                                    MPC107_MCC2_RMW_PAR_DATA


/* The Memory control Configuration  Register - 3  (MCCR3) */

#define MPC107_MCCR3_DEFAULT      ((MPC107_MCC3_BSTOPRE_DATA  << \
                                    MPC107_MCC3_BSTOPRE_25_S ) & \
                                    MPC107_MCC3_BSTOPRE_25_M)| \
                                  ((MPC107_MCC3_REFREC_DATA << \
                                    MPC107_MCC3_REFREC_SHIFT) & \
                                    MPC107_MCC3_REFREC_MASK) | \
                                  ((MPC107_MCC3_CPX_DATA << \
                                    MPC107_MCC3_CPX_SHIFT) & \
                                    MPC107_MCC3_CPX_MASK ) | \
                                  ((MPC107_MCC3_RAS6P_DATA << \
                                    MPC107_MCC3_RAS6P_SHIFT) & \
                                    MPC107_MCC3_RAS6P_MASK ) | \
                                  ((MPC107_MCC3_CAS5_DATA << \
                                    MPC107_MCC3_CAS5_SHIFT ) & \
                                    MPC107_MCC3_CAS5_MASK) | \
                                  ((MPC107_MCC3_CP4_DATA << \
                                    MPC107_MCC3_CP4_SHIFT) & \
                                    MPC107_MCC3_CP4_MASK) | \
                                  ((MPC107_MCC3_CAS3_DATA << \
                                    MPC107_MCC3_CAS3_SHIFT) & \
                                    MPC107_MCC3_CAS3_MASK ) | \
                                  ((MPC107_MCC3_RCD2_DATA << \
                                    MPC107_MCC3_RCD2_SHIFT ) & \
                                    MPC107_MCC3_RCD2_MASK) | \
                                  ((MPC107_MCC3_RP1_DATA << \
                                    MPC107_MCC3_RP1_SHIFT) & \
                                    MPC107_MCC3_RP1_MASK)




/*  Memory control Configuration  Register -4 (MCCR4) */

#define MPC107_MCCR4_DEFAULT       (MPC107_MCC4_PRETOACT_DATA << \
                                    MPC107_MCC4_PRETOACT_SHIFT) | \
                                   (MPC107_MCC4_ACTOPRE_DATA <<\
                                    MPC107_MCC4_ACTOPRE_SHIFT) | \
                                   (MPC107_MCC4_ACTOPRE_DATA << \
                                    MPC107_MCC4_ACTOPRE_SHIFT) | \
                                   (MPC107_MCC4_WMODE_DATA << \
                                    MPC107_MCC4_WMODE_SHIFT) | \
                                   (MPC107_MCC4_WMODE_DATA << \
                                    MPC107_MCC4_WMODE_SHIFT)| \
                                   (MPC107_MCC4_WMODE_DATA << \
                                    MPC107_MCC4_WMODE_SHIFT) | \
                                    MPC107_MCC4_BUFTYPE_DATA | \
                                  ((MPC107_BSTOPRE_DATA & \
                                    MPC107_MCC4_BSTOPRE_01_MASK) << \
                                    MPC107_MCC4_BSTOPRE_01_SHIFT)  | \
                                   (MPC107_BSTOPRE_DATA & \
                                    MPC107_MCC4_BSTOPRE_69_MASK) | \
                                  ((MPC107_MCC4_SDMODE_DATA << \
                                    MPC107_MCC4_SDMODE_SHIFT) & \
                                    MPC107_MCC4_SDMODE_MASK) | \
                                  ((MPC107_MCC4_ACTORW_DATA << \
                                    MPC107_MCC4_ACTORW_MASK) & \
                                    MPC107_MCC4_ACTORW_MASK)

/* SDRAM Page mode register initial value. */

#define MPC107_MPMR_DEFAULT	0x0032	/* SDRAM, 33Mhz w/ROMFAL =8 */


#ifdef __cplusplus
}
#endif

#endif	/* __INCmpc107MemInith */