ncr810.h

IXP425的BSP代码

#define     STEST1_QSEL  0x04   /* Quadrupler Select: Increase clock to 160 MHz */

/* STEST2 SCSI Test Two (RW) */

#define     STEST2_SCE   0x80	/* SCSI Control Enable */
#define     STEST2_ROF   0x40  	/* Reset SCSI OFfset */

#define     STEST2_DIF   0x20   /* NCR825 specific: SCSI Differential Mode */
#define     STEST2_AWS   0x04   /* NCR825 specific: Always Wide SCSI */

#define     STEST2_SLB   0x10 	/* SCSI Loopback Mode */
#define     STEST2_SZM 	 0x08	/* SCSI High Impedence Mode */
#define     STEST2_EXT	 0x02	/* Extend SREQ/SACK filtering - Should not be
				   set during FAST SCSI > 5MB/s */
#define     STEST2_LOW	 0x01	/* SCSI LOW level mode; no DMA operation occur
				   and no SCRIPTS execute */

/* STEST3 SCSI Test Three (RW) */

#define     STEST3_TE    0x80	/* Tolerant Enable */ 
#define     STEST3_STR   0x40	/* SCSI FIFO Test Read */
#define     STEST3_HSC	 0x20	/* Halt Scsi Clock */
#define     STEST3_DSI	 0x10	/* Disable Single Initiator response (SCSI-1) */
#define     STEST3_TTM	 0x04	/* Timer Test Mode */
#define     STEST3_CSF   0x02	/* Clear Scsi Fifo */
#define     STEST3_STW   0x01	/* SCSI Fifo Test Write */

/* STEST4 SCSI Test Four (RW) */

#define     STEST4_SMODE1    0x80	/* SCSI Mode Detect (upper bit) */
#define     STEST4_SMODE0    0x40	/* SCSI Mode Detect (lower bit) */
#define     STEST4_LOCK      0x20	/* Detect Clock Quadrupler Lockup */


/* Two types of register base address. Memory I/O and Cofig base addresses */

#define MEMIO_REG_BASE  (0x00)
#define CONFIG_REG_BASE (0x80)
#define BASE MEMIO_REG_BASE

/* _BYTE_ORDER is LITTLE_ENDIAN for PCI devices */

#define OFF_SCNTL0      (BASE) 		/* SCTNL0 SCSI control register 0 */
#define OFF_SCNTL1      (BASE + 0x01)	/* SCTNL1 SCSI control register 1 */
#define OFF_SCNTL2      (BASE + 0x02)	/* SCTNL2 SCSI control register 2 */
#define OFF_SCNTL3      (BASE + 0x03)	/* SCTNL3 SCSI control register 3 */
#define OFF_SCID	(BASE + 0x04)	/* SCID SCSI chip ID register */
#define OFF_SXFER	(BASE + 0x05)	/* SXFER SCSI chip ID regiester */
#define OFF_SDID	(BASE + 0x06)	/* SDID SCSI destination ID register */
#define OFF_GPREG	(BASE + 0x07)	/* GPREG General Purpose register */
#define OFF_SFBR	(BASE + 0x08)	/* SFBR SCSI first byte received reg */
#define OFF_SOCL	(BASE + 0x09) 	/* SOCL SCSI output control latch reg */
#define OFF_SSID	(BASE + 0x0a)	/* SSID SCSI selector ID */
#define OFF_SBCL	(BASE + 0x0b)	/* SBCL SCSI bus control lines reg */
#define OFF_DSTAT 	(BASE + 0x0c)	/* DSTAT DMA status register */
#define OFF_SSTAT0	(BASE + 0x0d)	/* SSTAT0 SCSI status register 0 */
#define OFF_SSTAT1	(BASE + 0x0e)	/* SSTAT1 SCSI status register 0 */
#define OFF_SSTAT2	(BASE + 0x0f)	/* SSTAT2 SCSI status register 0 */
#define OFF_DSA 	(BASE + 0x10)	/* DSA data structure address */
#define OFF_ISTAT   	(BASE + 0x14)	/* ISTAT interrupt status register */
#define OFF_CTEST0	(BASE + 0x18)	/* CTEST0 chip test register 0 */
#define OFF_CTEST1	(BASE + 0x19)	/* CTEST1 chip test register 1 */
#define OFF_CTEST2	(BASE + 0x1a)	/* CTEST2 chip test register 2 */
#define OFF_CTEST3	(BASE + 0x1b)	/* CTEST3 chip test register 3 */
#define OFF_TEMP  	(BASE + 0x1c)	/* TEMP temporary holding register */
#define OFF_DFIFO	(BASE + 0x20)	/* DFIFO DMA FIFO control register */
#define OFF_CTEST4	(BASE + 0x21)	/* CTEST4 chip test register 4 */
#define OFF_CTEST5	(BASE + 0x22)	/* CTEST5 chip test register 5 */
#define OFF_CTEST6	(BASE + 0x23)	/* CTEST6 chip test register 6 */
#define OFF_DBC 	(BASE + 0x24) 	/* DBC SIOP command register 24bits  */
#define OFF_DCMD	(BASE + 0x27)	/* DCMD SIOP command reg (8Bits Reg) */
#define OFF_DNAD	(BASE + 0x28)	/* DNAD DMA buffer ptr (next address) */
#define OFF_DSP 	(BASE + 0x2c)	/* DSP SIOP scripts pointer register */
#define OFF_DSPS	(BASE + 0x30)	/* DSPS SIOP scripts ptr save reg */
#define OFF_SCRATCHA0	(BASE + 0x34)	/* SCRATCHA0 gen purpose scratch reg */
#define OFF_SCRATCHA1	(BASE + 0x35)	/* SCRATCHA1 gen purpose scratch reg */
#define OFF_SCRATCHA2	(BASE + 0x36)	/* SCRATCHA2 gen purpose scratch reg */
#define OFF_SCRATCHA3	(BASE + 0x37)	/* SCRATCHA3 gen purpose scratch reg */
#define OFF_DMODE	(BASE + 0x38)	/* DMODE DMA operation mode register */
#define OFF_DIEN 	(BASE + 0x39)	/* DIEN DMA interrupt enable */
#define OFF_DWT  	(BASE + 0x3a)	/* DWT DMA watchdog timer register */
#define OFF_DCNTL	(BASE + 0x3b)	/* DCTNL DMA control register */	
#define OFF_ADDER	(BASE + 0x3c) 	/* ADDER Adder output Register */	
#define OFF_SIEN0	(BASE + 0x40)	/* SIEN0 SCSI interrupt enable 0 reg */
#define OFF_SIEN1	(BASE + 0x41)	/* SIEN1 SCSI interrupt enable 1 reg */
#define OFF_SIST0	(BASE + 0x42)	/* SIST0 SCSI interrupt status 0 reg */
#define OFF_SIST1	(BASE + 0x43)	/* SIST1 SCSI interrupt status 1 reg */
#define OFF_SLPAR	(BASE + 0x44)	/* SLPAR SCSI longitudinal Parity reg */
#define OFF_SWIDE	(BASE + 0x45)	/* NCR825: SWIDE SCSI Wide Residue */
#define OFF_MACNTL	(BASE + 0x46)	/* MACNTL Memory Access Control reg */
#define OFF_GPCNTL	(BASE + 0x47)	/* GPCNTL General Purpose Pin Control */
#define OFF_STIME0	(BASE + 0x48)	/* STIME0 SCSI Timer Zero reg */
#define OFF_STIME1	(BASE + 0x49)	/* STIME1 SCSI Timer One reg */
#define OFF_RESPID	(BASE + 0x4a)	/* RESPID Response ID reg */
#define OFF_STEST0	(BASE + 0x4c)	/* STEST0 SCSI Test 0 reg */
#define OFF_STEST1	(BASE + 0x4d)	/* STEST1 SCSI Test 1 reg */
#define OFF_STEST2	(BASE + 0x4e)	/* STEST2 SCSI Test 2 reg */
#define OFF_STEST3	(BASE + 0x4f)	/* STEST3 SCSI Test 3 reg */
#define OFF_SIDL	(BASE + 0x50)	/* SIDL SCSI input data latch reg */

#define OFF_STEST4	(BASE + 0x52)	/* STEST4 SCSI Test 4 reg */

#define OFF_SODL 	(BASE + 0x54)	/* SCSI output data latch reg */
#define OFF_SBDL 	(BASE + 0x58)	/* SBDL SCSI bus data lines register */
#define OFF_SCRATCHB	(BASE + 0x5c)	/* SCRATCHB Scratch Register B */

#define OFF_SCRATCHC	(BASE + 0x60)	/* SCRATCHC Scratch Register C */
#define OFF_SCRATCHD	(BASE + 0x64)	/* SCRATCHD Scratch Register D */
#define OFF_SCRATCHE	(BASE + 0x68)	/* SCRATCHE Scratch Register E */
#define OFF_SCRATCHF	(BASE + 0x6c)	/* SCRATCHF Scratch Register F */
#define OFF_SCRATCHG	(BASE + 0x70)	/* SCRATCHG Scratch Register G */
#define OFF_SCRATCHH	(BASE + 0x74)	/* SCRATCHH Scratch Register H */
#define OFF_SCRATCHI	(BASE + 0x78)	/* SCRATCHI Scratch Register I */
#define OFF_SCRATCHJ	(BASE + 0x7C)	/* SCRATCHJ Scratch Register J */

#define NCR810_DEVICE_ID   0x0001
#define NCR825_DEVICE_ID   0x0003
#define NCR875_DEVICE_ID   0x000f
#define NCR895_DEVICE_ID   0x000c
#define SYM895_DEVICE_ID   NCR895_DEVICE_ID
#define PCI_ID_SYMBIOS 0x1000

/*
 * NOTICE: The macro PCI_TO_MEM_OFFSET is not to be used anymore.  It
 * is a BSP specific value, not an architectural value.  The BSP should
 * update the value ncr810PciMemOffset with the appropriate offset value.
 */

/*
 * When memory is accessed from the PCI bus, the addresses need to contain this
 * offset
 *
 * MAKE NO FURTHER CHANGES HERE SEE SPR 8540
 */ 

#ifndef PCI_TO_MEM_OFFSET
#   if (CPU == I960JX)
#	define PCI_TO_MEM_OFFSET  0x00000000
#   else
#	define PCI_TO_MEM_OFFSET 0x80000000
#   endif
#endif


/* Mask Values */

#define NCR810_COUNT_MASK    ((UINT)0x00ffffff) /* Mask 24 bit value in block */
                                                /* move description */
/* Shift values for "device" field in shared data structure */

#define NCR810_TARGET_BUS_ID_SHIFT  16	/* bits 23-16: specify target bus ID */
#define	NCR810_XFER_PARAMS_SHIFT     8	/* bits 15-08: copy of sxfer reg.    */
 
/* Sync offset and period (SXFER register) */

#define NCR810_MIN_REQ_ACK_OFFSET    1	/* Minimum sync offset        */
#define NCR810_MAX_REQ_ACK_OFFSET    8	/* Maximum sync offset        */
/* #define NCR810_MAX_REQ_ACK_OFFSET   31 /@ Maximum sync offset 875/895*/
#define NCR810_MIN_XFER_PERIOD      0	/* Minimum sync period (clks) */
#define NCR810_MAX_XFER_PERIOD      7	/* Maximum sync period (clks) */
#define NCR810_MIN_XFERP            4	/* Minimum value of xferp */
#define NCR810_MAX_XFERP           11 	/* Maximum value of xferp */

#define	NCR810_SYNC_XFER_PERIOD_SHIFT 	5

#define	NCR810_SYNC_XFER_PARAMS_ASYNC	0x00

/* Synchronous transfer clock division factor (SBCL register bits 1,0 (w-o) */

#define	NCR810_MIN_CLOCK_DIV	    	0x00
#define	NCR810_MAX_CLOCK_DIV	    	0x03
#define	NCR810_CLOCK_DIVIDE_ASYNC   	0x00

/* Clock conversion factor */

/* prescale factor for asynchronous scsi core (scntl3) */

#define NCR810_16MHZ_ASYNC_DIV        0x01    /* 16.67-25.00Mhz input clock */
#define NCR810_25MHZ_ASYNC_DIV        0x02    /* 25.01-37.50Mhz input clock */
#define NCR810_50MHZ_ASYNC_DIV        0x03    /* 37.51-50.00Mhz input clock */
#define NCR810_66MHZ_ASYNC_DIV        0x04    /* 50.01-66.00Mhz input clock */

#define NCR810_75MHZ_ASYNC_DIV        0x04    /* 50.01-75.00Mhz input clock */

/*
 * Note: 80 Mhz value also has bit for clock doubler
 * set. We have to enable clock doubler
 * as we enabled the clock quadrupler. haven't included support
 * for clock doubler yet.
 *
 * Note: When Ultra enable bit is set, the Tolerant Enable bit must be set
 * also. It is STEST3:TE (bit 7).
 *
 */

#define NCR810_80MHZ_ASYNC_DIV        0x85    /* 75.01-80.00Mhz input clock */

/* note 120 MHz normally not used */

#define NCR810_160MHZ_ASYNC_DIV       0x87    /* 160.00 Mhz input clock with 
                                                clock quadrupler and 40 Mhz 
                                                input clock                 */

/* ns x 100 clock period */

#define NCR810_1667MHZ  6000    /* 16.67Mhz chip */
#define NCR810_20MHZ    5000    /* 20Mhz chip */
#define NCR810_25MHZ    4000    /* 25Mhz chip */
#define NCR810_3750MHZ  2667    /* 37.50Mhz chip */
#define NCR810_40MHZ    2500    /* 40Mhz chip */
#define NCR810_50MHZ    2000    /* 50Mhz chip */
#define NCR810_66MHZ    1515    /* 66Mhz chip */
#define NCR810_6666MHZ  1500    /* 66Mhz chip */
#define NCR810_75MHZ    1333    /* 75Mhz chip */
#define NCR810_80MHZ    1250    /* 80Mhz chip */
#define NCR810_160MHZ    625    /* 40Mhz chip with Quadrupler */


#define NCR810_MAX_SYNC_PERIOD   NCR810_50MHZ
#define NCR810_MAX_ASYNC_PERIOD  NCR810_25MHZ

/* for ncr875/895
#define NCR810_MAX_SYNC_PERIOD   NCR810_160MHZ
#define NCR810_MAX_ASYNC_PERIOD  NCR810_4MHZ
*/


#define NCR810_MAX_XFER_WIDTH 1	/* in transfer width exponent units. 16bits */

/* Chip Type */

#define NCR700_TYPE	0x700   /* not supported */
#define NCR810_TYPE	0x810   /* supported */
#define NCR720_TYPE	0x720   /* not supported */

/*
 * Default value to initialize some registers involved
 * in the hardware implementation.Those values could be
 * overwritten by a bsp call with the ncr810HwSetRegister().
 * The ncr810 Data Manual documentation will you give all
 * the light regarding values choose. See also the
 * documentation of ncr810SetHwRegister call.
 * See above the NCR810_HW_REGS for the meaning of the
 * values prefill.
 */

#define DEFAULT_810_HW_REGS {0,0,0,0,0,1,0,0,0,0,0}

/* function declarations */

IMPORT  NCR_810_SCSI_CTRL * ncr810CtrlCreate (
				UINT8 *siopBaseAdrs,
				UINT   clkPeriod, 
				UINT16 devType);

IMPORT  NCR_810_SCSI_CTRL * ncr810CtrlCreate2 (
				UINT8 *siopBaseAdrs,
				UINT   clkPeriod, 
				UINT16 devType,
				UINT8 *siopRamBaseAdrs,
				UINT8 *siopIOBaseAdrs);

IMPORT  STATUS  ncr810CtrlInit (NCR_810_SCSI_CTRL *pSiop, 
					int scsiCtrlBusId);
IMPORT	STATUS	ncr810SetHwRegister (NCR_810_SCSI_CTRL *pScsiCtrl,
				    NCR810_HW_REGS *pHwRegs);
IMPORT  void    ncr810Intr  (NCR_810_SCSI_CTRL *pSiop);
IMPORT  STATUS 	ncr810Show  (SCSI_CTRL *pScsiCtrl);
IMPORT  void    ncr810StepEnable (NCR_810_SCSI_CTRL *pSiop, BOOL enable);
IMPORT  void    ncr810SingleStep (NCR_810_SCSI_CTRL *pSiop, BOOL verbose);

#endif	/* _ASMLANGUAGE */
#ifdef __cplusplus
}
#endif

#endif /* __INCncr810h */